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JPH0530310B2 - - Google Patents

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Publication number
JPH0530310B2
JPH0530310B2 JP62311095A JP31109587A JPH0530310B2 JP H0530310 B2 JPH0530310 B2 JP H0530310B2 JP 62311095 A JP62311095 A JP 62311095A JP 31109587 A JP31109587 A JP 31109587A JP H0530310 B2 JPH0530310 B2 JP H0530310B2
Authority
JP
Japan
Prior art keywords
film
pattern
lower electrode
alo
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62311095A
Other languages
Japanese (ja)
Other versions
JPH01152775A (en
Inventor
Koji Yamada
Shinichiro Yano
Hiroyuki Mori
Yoshinobu Taruya
Mikio Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62311095A priority Critical patent/JPH01152775A/en
Publication of JPH01152775A publication Critical patent/JPH01152775A/en
Publication of JPH0530310B2 publication Critical patent/JPH0530310B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、極低温において動作するNb系ジヨ
セフソン接合素子のパターン形成方法に係り、特
に接合を構成する三層膜のパターン加工方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for patterning an Nb-based Josephson junction element that operates at extremely low temperatures, and particularly to a method for patterning a three-layer film constituting the junction.

〔従来の技術〕[Conventional technology]

従来のNb系ジヨセフソン接合素子は、特開58
−176983号公報に記載されている様に下部電極の
Nb膜、トンネル障壁層AlOx膜、上部電極のNb
膜を真空を破らずに三層膜を連続的に形成し、し
かる後にレジストをマスクにしドライエツチング
加工によつて所望とする接合および配線パターン
を形成する方法が取られていた。しかし、従来の
三層膜のエツチングでは上部電極と下部電極の
Nb膜はCF4ガスを用いた反応性イオンエツチン
グで加工し、トンネル障壁層のAlOx膜はArガス
を用いたイオンエツチングにより加工を行なつて
いた。このために下部電極のパターンエツジには
トンネル障壁層のAlOx膜がマスクとなつてアン
ダーカツトが形成されやすい構造であつた。さら
に、この後上部電極のNb膜で接合パターンを形
成しようとする際には、エツチング前から下部電
極のパターンエツジと下地の絶縁膜が露出してい
るためにアンダーカツトはより進行し、また、絶
縁膜もエツチングによつて膜減りを生じた。この
ために接合パターン加工後においてエツチング部
分を絶縁膜によつて埋戻す際に、下部電極のパタ
ーンエツジを完全に被覆することが困難であつ
た。この様なことから下部電極と上記電極接続配
線間において、しばしば短絡するという問題が発
生し回路動作に支障を来たしていた。
Conventional Nb-based Josephson junction elements are disclosed in Japanese Patent Application Laid-open No. 58
− As described in Publication No. 176983, the lower electrode
Nb film, tunnel barrier layer AlO x film, upper electrode Nb
A method has been used in which a three-layer film is continuously formed without breaking the vacuum, and then a desired bonding and wiring pattern is formed by dry etching using a resist as a mask. However, in conventional three-layer etching, the upper and lower electrodes are
The Nb film was processed by reactive ion etching using CF 4 gas, and the AlO x film of the tunnel barrier layer was processed by ion etching using Ar gas. For this reason, the AlO x film of the tunnel barrier layer serves as a mask at the pattern edge of the lower electrode, resulting in a structure in which undercuts are likely to be formed. Furthermore, when attempting to form a bonding pattern with the Nb film of the upper electrode after this, the pattern edge of the lower electrode and the underlying insulating film are exposed before etching, so undercutting progresses further. The thickness of the insulating film also decreased due to etching. For this reason, it has been difficult to completely cover the pattern edge of the lower electrode when backfilling the etched portion with an insulating film after processing the bonding pattern. As a result, short circuits often occur between the lower electrode and the electrode connection wiring, which hinders circuit operation.

〔発明が解決とようとする問題点〕[Problems that the invention attempts to solve]

第2図は、従来法により形成した Nb/AlOx/Nb三層膜のパターン形成工程を
示したものである。
FIG. 2 shows a pattern forming process of a Nb/AlO x /Nb three-layer film formed by a conventional method.

すなわち、第2図aにおいて、基板21上に
Nb膜より成る下部電極22、トンネル障壁層
AlOx23、Nb膜より成る上部電極24のNb/
AlOx/Nbの三層膜をスパツタ法で被着した。次
いで、第2図bにおいて、 AZ1350Jレジスト(米国ヘキスト社製商品名)
を用いて上部電極24上に接合部分と配線を含む
レジストパターン25を形成した。次いで、第2
図cにおいて、まず、上部電極24をAlOx23
の表面が露出するまでCF4ガスを用いた反応性イ
オンエツチングで加工をする。
That is, in FIG. 2a, on the substrate 21
Lower electrode 22 made of Nb film, tunnel barrier layer
AlO x 23, Nb/Nb of the upper electrode 24 made of Nb film
A three-layer film of AlO x /Nb was deposited by sputtering. Next, in FIG. 2b, AZ1350J resist (trade name manufactured by Hoechst, USA)
A resist pattern 25 including a bonding portion and wiring was formed on the upper electrode 24 using a method. Then the second
In Figure c, first, the upper electrode 24 is made of AlO x 23
Process by reactive ion etching using CF 4 gas until the surface is exposed.

次いで、トンネル障壁層のAlOx23をArガス
を用いたイオンエツチングで加工をし、下部電極
22の表面が露出した時点で、再び、CF4ガスを
用いた反応性イオンエツチングで下部電極22の
Nb膜が完全に除去されるまで加工を行つた。第
2図dはレジスト除去後の三層膜パターンの断面
図である。図で明らかな様に点線丸印内において
はAlOx23がマスクとなつて下部電極22がア
ンダカツトと成つている。また、上部電極24に
おいても下部電極22のエツチングの影響を受け
てアンダカツトが見られる。従つて、この様な断
面形状であると絶縁膜によるパターンエツジの被
覆も不完全と成り易く、層間絶縁膜の信頼性を著
しく低下することになる。このために三層膜のパ
ターン加工においてはアンダーカツトが形成され
ない様な構造を持つパターン加工方法が強く要望
されていた。
Next, the tunnel barrier layer AlO x 23 is processed by ion etching using Ar gas, and when the surface of the lower electrode 22 is exposed, the lower electrode 22 is etched again by reactive ion etching using CF 4 gas.
Processing was continued until the Nb film was completely removed. FIG. 2d is a cross-sectional view of the three-layer film pattern after resist removal. As is clear from the figure, within the dotted circle, the AlO x 23 serves as a mask and the lower electrode 22 forms an undercut. Also, undercuts are observed in the upper electrode 24 due to the etching of the lower electrode 22. Therefore, with such a cross-sectional shape, the pattern edges are likely to be incompletely covered by the insulating film, which significantly reduces the reliability of the interlayer insulating film. For this reason, in patterning a three-layer film, there has been a strong demand for a patterning method that has a structure that prevents the formation of undercuts.

本発明の目的は、層間絶縁膜を介して下部電極
と上部電極配線間で直接短絡が生じ得ない構造を
持つジヨセフソン接合素子のパターン形成方法を
提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a pattern of a Josephson junction element having a structure in which a direct short circuit cannot occur between a lower electrode and an upper electrode wiring via an interlayer insulating film.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、下部電極のNb膜だけを被着し、
その後、配線および接合部を含むパターンをテー
パエツチングにより加工することにより、達成さ
れる。その後、下部電極のNbパターン表面をAr
ガスによるスパツタクリーニングで清浄化し、ト
ンネル障壁層のAlOx膜、上部電極のNb膜を真空
を破らずに連続的に被着形成する。次いで、上部
電極のNb膜上に接合面積規定用のレジストマス
クを形成しCF4ガスを用いてエツチングを行なえ
ば所望とするジヨセフソン接合素子が得られる。
The above purpose is to deposit only the Nb film of the lower electrode,
This is then achieved by processing the pattern including the wiring and the bonding portion by taper etching. After that, the Nb pattern surface of the lower electrode was coated with Ar
It is cleaned by sputter cleaning with gas, and the AlO x film for the tunnel barrier layer and the Nb film for the upper electrode are continuously deposited without breaking the vacuum. Next, a resist mask for defining the junction area is formed on the Nb film of the upper electrode, and etching is performed using CF 4 gas to obtain the desired Josephson junction element.

〔作用〕[Effect]

本発明ではウエハー全面にAlOx膜が被着して
あるのでオーバエツチングの危険性も無く、プロ
セスの余裕度も広く取れる利点がある。すなわ
ち、下部電極のパターンにテーパが形成されてい
るために、AlOx膜の被覆性も充分であることか
ら下部電極パターンのアンダーカツトを皆無とす
ることが可能となつた。
In the present invention, since the AlO x film is deposited on the entire surface of the wafer, there is no risk of over-etching, and there is an advantage that the process can have a wide margin. That is, since the lower electrode pattern is tapered, the coverage of the AlO x film is sufficient, making it possible to completely eliminate undercuts in the lower electrode pattern.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面を用いて説明す
る。
An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明により形成したNb/AlOx
Nb系三層膜のパターン形成工程を示したもので
ある。
Figure 1 shows Nb/AlO x /
This figure shows the pattern formation process for a Nb-based three-layer film.

先ず、第1図aにおいて基板11上にNb膜よ
り成る下部電極12をスパツタ法で形成した。次
いで、第1図bにおいて、AZ1470レジスト(米
国ヘキスト社製商品名)を用いて下部電極12上
に接合部分と配線を含むレジストパターン13を
形成した。次いで、第1図cにおいて、CF4+10
%O2の混合ガスを用いた反応性イオンエツチン
グにより下部電極12のテーパエツチングを行つ
た。この際、CF4ガスに対してO2ガスの量を増す
ことによりテーパ角は小さく成る傾向にある。次
いで、第1図dにおいて、アセトンを用いてレジ
スト除去を行なつて下部電極12のパターンを形
成した。この時のテーパ角は30〜40度に成る様に
エツチング条件を設定した。次いで、第1図eに
おいて、下部電極12のNbパターンの表面をAr
ガスを用いたスパツタエツチングにより汚染層お
よび酸化層を完全に除去した後にトンネル障壁層
の AlOx膜14を被着形成し、次いで、真空を破
らずに上部電極15のNb膜を連続被着してジヨ
セフソン接合を構成する三層膜を形成した。図で
明らかな様に点線丸印内において、下部電極12
のNbパターンはテーパが形成されているために
AlOx膜14および上部電極15のNb膜は連続膜
と成つているのが分かる。したがつて、この
Nb/AlOx/Nbの三層膜構造であれば、次の接
合パターンを加工する時にAlOx膜ガストツパ材
と成り下部電極12はオーバエツチングから避け
られる。すなわち、下部電極12のNbパターン
のアンダカツトと下地基板11のオーバエツチン
グの問題を解決したことになる。この方法は従来
問題となつていた層間絶縁膜の被覆性の不充分差
を解消して下部電極と上部電極の接続配線間にお
ける短絡を完全に無くすることが出来た。
First, in FIG. 1a, a lower electrode 12 made of a Nb film was formed on a substrate 11 by sputtering. Next, in FIG. 1b, a resist pattern 13 including a bonding portion and wiring was formed on the lower electrode 12 using AZ1470 resist (trade name, manufactured by Hoechst, USA). Then, in Figure 1c, CF 4 +10
Taper etching of the lower electrode 12 was performed by reactive ion etching using a mixed gas of % O 2 . At this time, the taper angle tends to become smaller by increasing the amount of O 2 gas relative to CF 4 gas. Next, in FIG. 1d, the resist was removed using acetone to form a pattern for the lower electrode 12. Etching conditions were set so that the taper angle at this time was 30 to 40 degrees. Next, in FIG. 1e, the surface of the Nb pattern of the lower electrode 12 is coated with Ar.
After completely removing the contaminant layer and oxide layer by sputter etching using gas, the AlO x film 14 of the tunnel barrier layer is deposited, and then the Nb film of the upper electrode 15 is continuously deposited without breaking the vacuum. A three-layer film constituting a Josephson junction was then formed. As is clear from the figure, within the dotted circle, the lower electrode 12
Because the Nb pattern is tapered,
It can be seen that the AlO x film 14 and the Nb film of the upper electrode 15 are continuous films. Therefore, this
If the three-layer film structure is Nb/AlO x /Nb, the AlO x film will serve as a gas stopper material when processing the next bonding pattern, and the lower electrode 12 can be prevented from being over-etched. That is, the problems of undercutting of the Nb pattern of the lower electrode 12 and overetching of the underlying substrate 11 are solved. This method solves the conventional problem of insufficient coverage of the interlayer insulating film and completely eliminates short circuits between the connection wiring of the lower electrode and the upper electrode.

本発明により形成したNb/AlOx/Nb系ジヨ
セフソン接合素子の作製工程を第3図に示す。
FIG. 3 shows the manufacturing process of the Nb/AlO x /Nb type Josephson junction device formed according to the present invention.

先ず、第3図aにおいて、基板には直径50mmφ
のSi基板31を用いた。なお、Si基板31上には
層間絶縁膜のSiOが膜厚200nm被着してある。
First, in Figure 3a, the board has a diameter of 50mmφ.
A Si substrate 31 was used. Note that an interlayer insulating film of SiO is deposited on the Si substrate 31 to a thickness of 200 nm.

このSi基板31をスパツタ装置内に挿入して下
部電極32と成る膜厚200nmのNb膜をDCマグネ
トロンスパツタ法により被着した。被着条件は
Ar圧力0.6pa、堆積速度3nm/秒とした。
This Si substrate 31 was inserted into a sputtering device, and a 200 nm thick Nb film, which would become the lower electrode 32, was deposited by DC magnetron sputtering. The adhesion conditions are
The Ar pressure was 0.6 pa and the deposition rate was 3 nm/sec.

次いで、Si基板31をスパツタ装置から取り出
した後、まず、接合部分と配線と含むレジストパ
ターンを次の条件で形成した。AZ1470レジスト
(米国ヘキスト社商品名)を膜厚1.6μmをスピン
塗布により形成した。次いで、90℃、20分間のプ
リベーク後、光強度6mW/cm2の紫外光により12
秒間のパターン転写を行なつた。次いで、AZデ
ベロツパー:水=1:1の組成比で液温24℃中で
60秒間の現像処理を行つた。次いで、このSi基板
31をエツチング加工をするためにエツチング装
置内に挿入し、減圧した後CF4ガスによる反応性
イオンエツチングにより下部電極32のテーパエ
ツチング加工を行つた。加工条件は、CF4+20%
O2の混合ガスにより、圧力26pa、電力100Wで行
なつた、この時の下部電極32のパターンテーパ
角度は、配線パターン(2.5μm)も考慮して約35
度と成る様に条件を設定した。再び、エツチング
装置内より取り出してアセトンによりレジストを
除去した。次いで、ジヨセフソン接合を構成する
三層膜を形成するために、再び、スパツタ装置内
に挿入した。次いで、下部電極32のNbパター
ン表面の汚染層と酸化層を完全に除去するために
Arガスを用いてスパツタエツチングで清浄化処
理を行なつた。この時の条件はAr圧力0.8pa、電
力70W、処理時間20分で行なつた。次いで、トン
ネル障壁層を形成するために同一スパツタ装置内
のAlのターゲツト真下に移動してAlの膜厚5nm
被着した。Alの堆積速度は0.2nm/秒とした。Al
膜形成後スパツタ装置内にO2ガスを100pa導入し
室温(24〜26℃)中で40分間の自然酸化を行なつ
てAlの表面酸化膜であるAlOx膜33を形成した。
再び、スパツタ装置内を真空排気した後、Si基板
31をNbのターゲツト真下に移動し、DCマグネ
トロンスパツタ法により上記電極34のNb膜を
膜厚100nmを連続被着し三層膜を形成した。Si基
板31をスパツタ装置内から取り出した後、上部
電極34上に接合面積を規定するレジストパター
ンを次の条件で形成した。AZ1470レジストを膜
厚1.2μmをスピン塗布により形成した。次いで、
90℃、20分間のプリベーク後、密着露光により12
秒間のパターン転写を行なつた。接合面積は1.8
×1.8μm2である。次いで、第3図bにおいて、再
び、エツチング装置内に挿入し、減圧した後、
CF4ガスによる反応性イオンエツチングにより上
部電極34のNb膜のパターン加工をCF4ガス圧
力26pa、電力100Wの条件下で行なつた。この
際、オーバエツチングを行なつてもAlOx33が
全面に被着してあるためにストツパ材となり下部
電極32のNbパターンおよびSi基板31は、エ
ツチングによるダメージを受けることが無い。次
いで、第3図cにおいて、接合パターン上のレジ
ストをマスクにしエツチング部分の埋戻しを絶縁
膜により行なうために、再び、真空装置内へ挿入
し減圧した後、上部電極34の膜厚に比べて2割
程度厚くSiを用いた絶縁膜36により埋戻しを行
なつた。第3図dにおいて、再び、真空装置から
取り出してアセトンによりリフトオフを行なつて
エツチング部分を完全に埋戻し層間絶縁膜36と
した。次いで、第3図eにおいて、再びスパツタ
装置内に挿入して上部電極34の接合パターンの
表面を前述した下部電極の表面クリーニングと同
条件下でスパツタエツチング処理を行なつた。次
いで、上部電極34と接続配線を行なうために
Nb膜を膜厚300nm被着して配線電極膜とした。
Nb膜の被着条件は前述の下部電極32と同条件
でDCマグネトロンスパツタ法で被着した。再び、
スパツタ装置内から取り出した後、前述した下部
電極32と同条件でレジストパターンを形成し
た。次いで、再び、エツチング装置内に挿入し減
圧してから、前述した同条件でCF4ガスによる反
応性イオンエツチングによりレジストパターン以
外のNb膜をエツチング除去した。次いで、再び、
エツチング装置内により取り出してからアセトン
によりパターン上のレジストを除去し上部電極3
4に接続する配線電極37を形成した。
Next, after taking out the Si substrate 31 from the sputtering apparatus, first, a resist pattern including a bonding portion and wiring was formed under the following conditions. AZ1470 resist (trade name, Hoechst, USA) was formed by spin coating to a thickness of 1.6 μm. Next, after prebaking at 90℃ for 20 minutes, UV light with a light intensity of 6mW/ cm2 was used for 12 hours.
Pattern transfer was performed in seconds. Next, at a liquid temperature of 24°C at a composition ratio of AZ developer: water = 1:1.
A developing process was performed for 60 seconds. Next, this Si substrate 31 was inserted into an etching apparatus for etching, and after the pressure was reduced, the lower electrode 32 was tapered by reactive ion etching using CF 4 gas. Processing conditions are CF 4 +20%
The pattern taper angle of the lower electrode 32 at this time, which was performed using a mixed gas of O 2 at a pressure of 26 pa and a power of 100 W, was approximately 35 mm, taking into account the wiring pattern (2.5 μm).
The conditions were set so that the It was taken out of the etching apparatus again and the resist was removed with acetone. Next, it was inserted into the sputtering device again in order to form a three-layer film constituting a Josephson junction. Next, in order to completely remove the contamination layer and oxide layer on the Nb pattern surface of the lower electrode 32,
Cleaning treatment was performed by sputter etching using Ar gas. The conditions at this time were Ar pressure 0.8 pa, power 70 W, and processing time 20 minutes. Next, in order to form a tunnel barrier layer, the Al layer was moved to a layer directly below the Al target in the same sputtering device to form an Al film with a thickness of 5 nm.
It was covered. The Al deposition rate was 0.2 nm/sec. Al
After film formation, 100 pa of O 2 gas was introduced into the sputtering apparatus and natural oxidation was performed for 40 minutes at room temperature (24 to 26° C.) to form an AlO x film 33, which is a surface oxide film of Al.
After evacuating the inside of the sputtering device again, the Si substrate 31 was moved directly below the Nb target, and a 100 nm thick Nb film was continuously deposited as the electrode 34 using the DC magnetron sputtering method to form a three-layer film. . After taking out the Si substrate 31 from the sputtering apparatus, a resist pattern defining a bonding area was formed on the upper electrode 34 under the following conditions. AZ1470 resist was formed by spin coating to a thickness of 1.2 μm. Then,
After pre-baking at 90℃ for 20 minutes, 12
Pattern transfer was performed in seconds. Joint area is 1.8
× 1.8μm2 . Next, in FIG. 3b, after inserting into the etching apparatus again and reducing the pressure,
The Nb film of the upper electrode 34 was patterned by reactive ion etching using CF 4 gas under conditions of CF 4 gas pressure of 26 pa and power of 100 W. At this time, even if over-etching is performed, the Nb pattern of the lower electrode 32 and the Si substrate 31 will not be damaged by etching since the AlO x 33 is coated over the entire surface and serves as a stopper material. Next, in FIG. 3c, in order to backfill the etched portion with an insulating film using the resist on the bonding pattern as a mask, the film is inserted into the vacuum device again and the pressure is reduced. Backfilling was performed with an insulating film 36 made of Si and about 20% thick. In FIG. 3D, the film was taken out of the vacuum apparatus again and lifted off with acetone to completely backfill the etched portion to form an interlayer insulating film 36. Next, in FIG. 3e, the substrate was inserted into the sputtering apparatus again, and the surface of the bonding pattern of the upper electrode 34 was subjected to sputter etching under the same conditions as the surface cleaning of the lower electrode described above. Next, in order to perform connection wiring with the upper electrode 34.
A 300 nm thick Nb film was deposited to form a wiring electrode film.
The Nb film was deposited by DC magnetron sputtering under the same conditions as for the lower electrode 32 described above. again,
After taking it out from the sputtering apparatus, a resist pattern was formed under the same conditions as for the lower electrode 32 described above. Then, after inserting it into the etching apparatus again and reducing the pressure, the Nb film other than the resist pattern was etched away by reactive ion etching using CF 4 gas under the same conditions as described above. Then again,
After removing it from the etching equipment, remove the resist on the pattern with acetone and remove the upper electrode 3.
A wiring electrode 37 connected to 4 was formed.

以上の作製工程を経てNb/AlOx/Nb膜ジヨ
セフソン接合素子を作製した。なお、本実施例に
おいては埋戻し用の絶縁膜としてSiを用いたが
SiO,SiO2,Al2O3,MgO,Ge,MgF等を用い
ても同様の効果が得られる。また、超電導薄膜と
してNbを用いたが、本発明ではこれに限られる
ことはなく、NbN,MoN,TaN,TiN等を用
いても同様の効果が得られる。
Through the above manufacturing steps, an Nb/AlO x /Nb film Josephson junction device was manufactured. Note that in this example, Si was used as the insulating film for backfilling.
Similar effects can be obtained using SiO, SiO 2 , Al 2 O 3 , MgO, Ge, MgF, etc. Further, although Nb is used as the superconducting thin film, the present invention is not limited to this, and similar effects can be obtained by using NbN, MoN, TaN, TiN, etc.

例えば、256個直列に接続した1.7×1.7μm2のジ
ヨセフソン接合の超電導臨界電流(Ic)のバラツ
キ幅は±5〜6%以内で形成できる。このため、
回路の動作マージンも大幅に向上可能となつた。
また、本発明においては下部電極のNb膜に生ず
る内部応力も三層膜形成前にパターン加工をする
ために大半が緩和されることから接合特性のわず
かな劣化も見られなく成つた。
For example, 256 Josephson junctions of 1.7×1.7 μm 2 connected in series can be formed with variations in superconducting critical current (Ic) within ±5 to 6%. For this reason,
It has also become possible to significantly improve the operating margin of the circuit.
Furthermore, in the present invention, most of the internal stress generated in the Nb film of the lower electrode is relaxed because the patterning is performed before the formation of the three-layer film, so that no slight deterioration of the bonding properties was observed.

さらに、1.5×1.5μm2の十字型接合においても
256個直列に接続したIcのバラツキ幅は±3〜4
%以内であり電極間での短絡故障はまつたく見ら
れず、再現性の良い接合特性の結果が得られた。
Furthermore, even in a cruciform junction of 1.5 × 1.5 μm 2
The variation width of 256 ICs connected in series is ±3 to 4
%, there were no short-circuit failures between the electrodes, and results of bonding characteristics with good reproducibility were obtained.

〔発明の効果〕〔Effect of the invention〕

本発明により、従来問題となつていた層間絶縁
膜を介しての下部電極と上部電極配線間で生ずる
短絡故障は下部電極Nbパターンにテーパを形成
することにより皆無となつた。これと層間絶縁膜
の被覆性が完壁になつたために信頼性の高い Nb/AlOx/Nb系のジヨセフソン接合素子が
再現性良く形成出来ることが可能となつた。
According to the present invention, the short-circuit failure that occurs between the lower electrode and the upper electrode wiring via the interlayer insulating film, which has been a problem in the past, is completely eliminated by forming a taper in the lower electrode Nb pattern. This and the perfect coverage of the interlayer insulating film made it possible to form highly reliable Nb/AlO x /Nb-based Josephson junction elements with good reproducibility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のNb/AlOx/Nb系三層膜の
パターン形成工程を示す図、第2図は従来法の
Nb/AlOx/Nb系三層膜のパターン形成工程を
示す図、第3図は本発明で形成したNb/AlOx
Nb系ジヨセフソン接合素子の作製工程を示す図
である。 11,21,31……Si基板、12,22,3
2……下部電極、13,25,35……レジスト
パターン、14,23,33……トンネル障壁
層、15,24,34……上部電極、36……絶
縁膜、37……配線電極。
Figure 1 is a diagram showing the pattern formation process of the Nb/ AlO
A diagram showing the pattern formation process of Nb / AlO x /Nb-based three-layer film, FIG.
FIG. 3 is a diagram showing a manufacturing process of an Nb-based Josephson junction device. 11, 21, 31...Si substrate, 12, 22, 3
2... Lower electrode, 13, 25, 35... Resist pattern, 14, 23, 33... Tunnel barrier layer, 15, 24, 34... Upper electrode, 36... Insulating film, 37... Wiring electrode.

Claims (1)

【特許請求の範囲】 1 (1) 基板上に下部電極のNb膜を形成した後、
このNb膜上に配線および接合を含むレジスト
パターンを形成する工程、 (2) 上記Nb膜をドライエツチングによりテーパ
形状にパターン加工をする工程、 (3) 上記Nb膜パターンの表面をArスパツタクリ
ーニングにより清浄化をする工程、 (4) 上記Nbパターン上及び基板上に、トンネル
障壁層のAlOx膜、上部電極のNbを連続形成し
て部分的に三層膜を形成する工程、 (5) 上記三層膜上へ接合面積規定用のレジストパ
ターンを形成する工程、 (6) 上記上部電極Nb膜をドライエツチングによ
りパターン加工をする工程、 (7) 上記Nb膜上に残存したレジストをマスクに
しエツチング部分を絶縁膜により埋戻しを行う
工程、 (8) 上記上部電極Nb膜と接続をとるためのNb配
線電極を形成する工程を有することを特徴とす
るジヨセフソン接合素子のパターン形成方法。 2 特許請求の範囲第1項において、上記テーパ
形状のテーパ角は15〜75度の範囲であることを特
徴とするジヨセフソン接合素子のパターン形成方
法。
[Claims] 1 (1) After forming the Nb film of the lower electrode on the substrate,
Step of forming a resist pattern including wiring and bonding on this Nb film, (2) Step of patterning the above Nb film into a tapered shape by dry etching, (3) Cleaning the surface of the above Nb film pattern with Ar sputtering. (4) Step of sequentially forming an AlO x film as a tunnel barrier layer and Nb as an upper electrode on the Nb pattern and the substrate to partially form a three-layer film; (5) (6) forming a pattern on the upper electrode Nb film by dry etching; (7) using the resist remaining on the Nb film as a mask; A method for forming a pattern of a Josephson junction element, comprising the steps of: backfilling the etched portion with an insulating film; and (8) forming a Nb wiring electrode for connection with the upper electrode Nb film. 2. The method for forming a pattern of a Josephson junction element according to claim 1, wherein the taper angle of the tapered shape is in the range of 15 to 75 degrees.
JP62311095A 1987-12-10 1987-12-10 Forming method of pattern of josephson junction device Granted JPH01152775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62311095A JPH01152775A (en) 1987-12-10 1987-12-10 Forming method of pattern of josephson junction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62311095A JPH01152775A (en) 1987-12-10 1987-12-10 Forming method of pattern of josephson junction device

Publications (2)

Publication Number Publication Date
JPH01152775A JPH01152775A (en) 1989-06-15
JPH0530310B2 true JPH0530310B2 (en) 1993-05-07

Family

ID=18013074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62311095A Granted JPH01152775A (en) 1987-12-10 1987-12-10 Forming method of pattern of josephson junction device

Country Status (1)

Country Link
JP (1) JPH01152775A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111306A (en) * 2007-11-01 2009-05-21 Hitachi Ltd Electronic device with Josephson junction and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58176983A (en) * 1982-04-12 1983-10-17 Agency Of Ind Science & Technol Preparation of jusephson junction device
JPS6233483A (en) * 1985-08-07 1987-02-13 Agency Of Ind Science & Technol Superconductive integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58176983A (en) * 1982-04-12 1983-10-17 Agency Of Ind Science & Technol Preparation of jusephson junction device
JPS6233483A (en) * 1985-08-07 1987-02-13 Agency Of Ind Science & Technol Superconductive integrated circuit

Also Published As

Publication number Publication date
JPH01152775A (en) 1989-06-15

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