JPS6230352A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS6230352A JPS6230352A JP60168872A JP16887285A JPS6230352A JP S6230352 A JPS6230352 A JP S6230352A JP 60168872 A JP60168872 A JP 60168872A JP 16887285 A JP16887285 A JP 16887285A JP S6230352 A JPS6230352 A JP S6230352A
- Authority
- JP
- Japan
- Prior art keywords
- current
- projection
- peripheral edge
- metal frame
- cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置用パッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a package for a semiconductor device.
従来、半導体装置用パッケージの気密封止として、″電
気抵抗溶接を利用した封止が一般に行なわれている。第
６図に示すように、バラケーン部材として周線部［Ａｙ
Ｃ，ろう材などでろう熾した金属フレーム２を有する
セラはツク基盤３と、金属キャップ１と？用意する。十
尋坏チップ４をセラミック基盤６の凹所に接着してから
、ボンディング線５で外部リード６との電気接続をなし
てから、金属キャップ１全金属フレーム２の上に配置す
る。そして、両者全上方から一対のローラ電極７で圧着
しつつ、電極間に電流全波すことで、発生するジュール
熱で溶接する。この気密封止は溶接時に、半導体チップ
４が加熱されないという利点がある。Conventionally, as a hermetic seal for semiconductor device packages, sealing using electric resistance welding has generally been performed.As shown in FIG.
C. Is the ceramic having a metal frame 2 soldered with a brazing material etc. a base plate 3 and a metal cap 1? prepare. After adhering the ten-layer chip 4 to the recess of the ceramic substrate 6 and making electrical connection with the external lead 6 using the bonding wire 5, the metal cap 1 is placed on the all-metal frame 2. Then, while both are pressed together from above with a pair of roller electrodes 7, a full wave of current is applied between the electrodes, and the Joule heat generated is used to weld. This hermetic sealing has the advantage that the semiconductor chip 4 is not heated during welding.
上記溶接法は、溶接部以外のキャップへ流扛る電流が多
く、電流効率が良くないので、しにしは浴炭不良の事故
が発生する。こｎを防ぐため、大を流を流すと、キャッ
プが過熱さ７′Ｌ変色するなどの不部会が生ずる。通正
に気密封止全行なう電流条件の範囲が狭く、パッケージ
の材質形状などのバラツキを考慮して条件設定ケ行なう
ことが難しかった。In the above-mentioned welding method, a large amount of current flows to the cap other than the welded part, and the current efficiency is not good, so accidents of poor bath coal often occur. In order to prevent this, if a large amount of water is passed through the cap, problems such as discoloration of the cap due to overheating will occur. The range of current conditions that would normally achieve complete hermetic sealing was narrow, and it was difficult to set the conditions while taking into account variations in the material and shape of the package.
キャップを薄くすれば、キャップ全波ｎる電流成分の比
率が少なくなジ、＃接成流を小さくできるが、気密性の
確認のために行なう気密性試験の予備段階で加える圧力
［酎えらｎずキャップが変形する。変形によって商品と
して外貌不良になるばかりでなく、捺印の文字がうまく
捺印さｎない不良も発生する。If the cap is made thinner, the proportion of the current component in the cap's full wave will be reduced, and the contact flow can be made smaller. The cap is deformed. The deformation not only causes the product to look defective, but also causes defects in which the characters are not stamped properly.
本発明の目的は、上記の欠点全除去し、電気抵抗溶接を
効果的に行なうことのできる半導体装置用パッケージ全
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a complete package for a semiconductor device which can eliminate all of the above-mentioned drawbacks and can effectively perform electric resistance welding.
本発明の手勢用装置用パッケージげ、セラミック基盤の
周縁部に設けた金属フレームの外周線に、突起を設け、
金属キャップとの気密封止において、この部分全電気抵
抗浴接によって耐層するようにする。The package for a hand-held device of the present invention includes a protrusion provided on the outer circumferential line of the metal frame provided at the periphery of the ceramic base,
In hermetically sealing with the metal cap, this part is made to have a layer resistance through electrical resistance bath welding.
全域フレームの外周縁に設けた突起に、′電流が集中し
て流れ、しかもこの部分は断面積が狭く抵抗が高くなる
ので、小を流でも溶接に必要なジュール熱が発生する。Current flows in a concentrated manner through the protrusions provided on the outer periphery of the entire area frame, and since this portion has a narrow cross-sectional area and high resistance, even a small current generates the Joule heat necessary for welding.
したがってＲＬ流を従来よシ小さくしても充分な信頼度
の商い耐層が可能になる。Therefore, even if the RL flow is made smaller than in the past, it is possible to achieve a commercial layer with sufficient reliability.
以下、図面に参照して本発明の実施例について説明する
。第１図が一実施例の説明のための図である。パッケー
ジ部材として、セラミック基盤３の周縁部にろう接した
金属フレーム１０法図示のように外周縁に突起１０ａ
ｆ有している。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining one embodiment. As a package member, a metal frame 10 is soldered to the periphery of the ceramic substrate 3.Protrusions 10a are provided on the outer periphery as shown in the figure.
It has f.
封止作業は全〈従来どおりに行なう。ローラ電極７′に
回転しながら、突起１０ａと金属キャップ１との接触部
全押しつけ、電極間に電流を流す。ジュール熱の発生は
殆ど突起１０ａの接７！！部で生ずるから、電流が少な
くても十分のろう接強度を得ることができる。All sealing work is carried out as before. While rotating, the roller electrode 7' is pressed against the entire contact area between the protrusion 10a and the metal cap 1, and a current is passed between the electrodes. Most of the Joule heat is generated at the contact 7 of the protrusion 10a! ! Therefore, sufficient soldering strength can be obtained even with a small current.
次に第２の実施例として、電極の構造を変えた場合につ
いて述べる。第２図に示すようｔｒｉｌｌ方のｔ極１１
Ａが上方から、他方の電極１１Ｂが金属フレーム１０の
側面から接触するようにしである。電極１１Ａからの電
流は戴椙キャッグ１の周縁部をとおり、金桶フレーム１
ｏの突起１０ａ ”ｆ経て１．を極１１Ｂに流れる。こ
の電極４造は、従来の回転′ＲＬ極の場合に対し外周全
同時に浴接できるので作業時間が低減する利点がある・
また金属キャップ１を流れる電流は丁度突起１０ａｉＣ
あたる浴接部位のみしか流れないので、キャップの厚み
Ｖｉ電流効率に影響しない。したがってキャップ厚みは
機械的強度全考慮して所望の板厚とすることができる。Next, as a second example, a case will be described in which the structure of the electrode is changed. As shown in FIG. 2, the t-pole 11 on the trill side
A contacts the metal frame 10 from above, and the other electrode 11B contacts the metal frame 10 from the side. The current from the electrode 11A passes through the periphery of the Daishu cag 1,
Flows through the protrusion 10a of o and 1. to the pole 11B.This four-electrode structure has the advantage that the entire outer circumference can be brought into contact with the bath at the same time, which reduces the working time, compared to the case of the conventional rotating RL pole.
Also, the current flowing through the metal cap 1 is exactly the protrusion 10aiC.
The cap thickness Vi does not affect the current efficiency because the current flows only in the bath contact area. Therefore, the thickness of the cap can be set to a desired thickness with full consideration of mechanical strength.
以上、説明したように、本発明のパッケージはセラミッ
ク基察の周縁部に設けた金属フレームの突起部分に電流
が集中しこの部分で溶接されるので、電流効率が良い酊
接を行なうことができる。したがって従来のように、電
流効率が低いの？カバーするため、電流値を大きくシー
Ｃキャップを過熱変色させる事故は生じな−。As explained above, in the package of the present invention, current is concentrated on the protruding part of the metal frame provided at the periphery of the ceramic base and welding is performed at this part, so welding can be performed with high current efficiency. . Therefore, is the current efficiency as low as in the past? In order to cover this, the current value is increased to avoid the accident of overheating and discoloration of the Sea C cap.
また、実施例に示すように、グロジエクション俗接が可
能ＶＣなや、キャップの板厚ケ厚くすることができる。In addition, as shown in the embodiments, the cap can be made thicker if the VC can be used for general glossejection.
４、１聞のｒ１ＰＪ単な説明
第１図、第２図は本発明の実砲圀でるるパッケージの浴
接作業ケ説明するための図、第３図は従来例の場合を示
す図である。4. Simple explanation of r1PJ in 1st episode Figures 1 and 2 are diagrams for explaining the bath welding work of the Ruru package in the actual gun field of the present invention, and Figure 3 is a diagram showing the case of a conventional example. .
１・・・金属キャップ、 ２・・・金属フレーム（
従来例）、５・・・セラミック基盤、 １ｏ・・・
金属フレーム（本発明）、１０ａ・・・突起、
７・・・ローラ゛電極、ｊＩＡ、 １１Ｂ・・・電極
。1...Metal cap, 2...Metal frame (
Conventional example), 5... Ceramic base, 1o...
Metal frame (present invention), 10a... protrusion,
7... Roller electrode, jIA, 11B... Electrode.
特許出願人 日本電気株式会社 １５１．、ン、Patent applicant: NEC Corporation 151. ,hmm,
Claims (1)
ャップを気密封止するパッケージにおいて、該金属フレ
ームの外周縁に、電気抵抗溶接によつて金属キャップと
封着される突起を設けたことを特徴とする半導体装置用
パッケージ。A package in which a metal cap is hermetically sealed to a metal frame provided at the periphery of a ceramic substrate, characterized in that a protrusion is provided on the outer periphery of the metal frame to be sealed to the metal cap by electric resistance welding. Packages for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60168872A JPS6230352A (en) | 1985-07-31 | 1985-07-31 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60168872A JPS6230352A (en) | 1985-07-31 | 1985-07-31 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6230352A true JPS6230352A (en) | 1987-02-09 |
Family
ID=15876125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60168872A Pending JPS6230352A (en) | 1985-07-31 | 1985-07-31 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6230352A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274054A (en) * | 1988-09-09 | 1990-03-14 | Nec Kyushu Ltd | Sealing method of semiconductor device |
| US5729179A (en) * | 1995-09-28 | 1998-03-17 | Sanyo Electric Co., Ltd. | Variable Frequency Divider |
-
1985
- 1985-07-31 JP JP60168872A patent/JPS6230352A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274054A (en) * | 1988-09-09 | 1990-03-14 | Nec Kyushu Ltd | Sealing method of semiconductor device |
| US5729179A (en) * | 1995-09-28 | 1998-03-17 | Sanyo Electric Co., Ltd. | Variable Frequency Divider |
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