JPS62296456A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the isolation groove width to be narrow by performing ion implantation with a well pattern and the side wall formed on the side wall thereof as a mask, filling up the well region, thereafter removing the side wall portion, and forming therein a groove for isolation. CONSTITUTION:An oxide film 22 is formed on a P-type silicon substrate 21, and an opening portion is formed. An oxide film 23 is deposited on the opening portion by means of thermal oxidation, and a poly-silicon film 24 is deposited on the oxide films 22, 23. Then, a side wall of the poly-silicon 24 is formed on the side wall of the oxide film 22, and phosphorus 25 is implanted. After applying a photoresist 26 and flattening the surface of the pattern, etching is carried out till the poly-silicon 24 is exposed. With the oxide film 22 and the photoresist 26 as a mask the poly-silicon 24, oxide film 23 and P-type silicon substrate 21 are etched, thereby forming a groove 27 for well isolation.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Industrial Application Field) This invention is a CMO device that uses buried-trench isolation to isolate an NMOS transistor region and a PMOS transistor region.
8 relates to a method for manufacturing a semiconductor device.

(Prior Art) FIGS. 2(a) to 2(d) show the conventional manufacturing process of trench-filling isolation technology in the case of a well-type CMO8. A conventional manufacturing process will be explained with reference to FIGS. 2(a) to 2(d).

First, as shown in FIG. 2(a), a pattern is formed on a P-type silicon 11 using a photoresist 12, and P (phosphorus) 13 is introduced by ion implantation.

Next, as shown in FIG. 2(b), an N-type well 14 is formed by heat treatment.

Thereafter, as shown in FIG. 2(c), a pattern is formed with photoresist 12 at the boundary between the N-type well 14 region and the P-type silicon substrate 11, and a groove 15 for isolation is formed by etching. do.

Next, as shown in FIG. 2(d), a CV
By depositing and burying the D oxide film 16, trench-embedded isolation can be achieved between the N-type well 14, which is a PMOS transistor region, and the P-type silicon substrate 11, which is an NMOS transistor region.

(Problem to be solved by the invention) However, in such a conventional manufacturing method, the N-type well 1
4 and the groove 15 are required, and between the lateral diffusion of impurity atoms in the N-type well 14 by heat treatment and the two photolithography steps. It was necessary to design grooves and setters that took into account alignment accuracy, making it difficult to narrow the separation groove width.

This invention solves the problems of the above-mentioned prior art.
The present invention provides a semiconductor device that solves the problems of accuracy in lateral diffusion of impurities in an N-type well and two photorin steps, and difficulty in narrowing the isolation groove width.

(Friendly means of solving problems) The present invention relates to a method for manufacturing a semiconductor device.

After forming the well non-turn on the side wall and performing ion implantation using the trench as a mask, the side wall
This method introduces a step of removing the groove and forming a separation groove in that area.

(Function) According to the present invention, in a method for manufacturing a semiconductor device, since the above steps are introduced, ions of impurity atoms are implanted into a region that will become a well using a sidewall as a mask, and the ions are implanted. After that, the mask is removed, and grooves are formed in the removed portions of the seven masks in self-alignment with the wells.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
h) is a process explanatory diagram of the example.

First, as shown in FIG. 1(a), a P-type silicon substrate 2
1, an oxide film 22 of 7000 nm is formed by thermal oxidation or CVDK.
~15,000 layers are formed, and the oxide film in the area where the well will be formed is removed through a photorin etching process, which has different etching characteristics from silicon, to form an opening.Next, as shown in Figure 1(b), As shown, an oxide film 2 is formed by thermal oxidation in the above-mentioned opening to serve as an etching mask for the next process.
3 with a thickness of 500 to 1000λ. This oxide film 23 has a different etching rate from that of the oxide film 22. Next, the F)de silicon film 24 is deposited by CVD to 4000 to 200%
000^ is deposited on the oxide film 22.23.

Next, as shown in FIG. 1(e), a side wall of polysilicon 24 with a thickness of 0.3 to 2.0 μm is formed on the side wall of the oxide film 22 by anisotropic etching to form an N-type well. In order to
KeV, dose 1t1011~101410n3
/c! Ion implantation is performed at A.

Next, as shown in FIG. 1(d) K, oxide films 22 and 23 are formed.
A photoresist 26 having different etching characteristics from that of the etching process is applied, and after the four turns are made flat, the photoresist 26 is etched until the silicon 24 is exposed as shown in FIG. 1(6).

Next, as shown in FIG. 1<0, polysilicon 24,
The oxide film 23 and the P-type silicon substrate 21 are etched to form W427 for well isolation.

Next, as shown in FIG. 1(g), after removing the oxide film 22, photoresist 26 and oxide film 23 by etching,
The trench 27 is filled with an oxide film 28 formed by CVD.

Next, as shown in FIG. 1(h), the ion-implanted phosphorus 25tl is diffused by heat treatment to form an N well 29.

(Effects of the Invention) As described above in detail, according to the present invention, ions are implanted into the entire mask of the sidewall formed on the well pattern and its sidewall, and after burying the fell region, the sidewall portion is removed and the sidewall portion is removed. Since the trench for isolation is formed in the well, the trench for well isolation is formed in self-alignment with the well.

Furthermore, the width of the separation groove is determined by the width of the sidewall.Ninth, it is also possible to form a very narrow separation groove.

[Brief explanation of drawings]

1(a) to 1Ql) are process explanatory diagrams of an embodiment of the semiconductor device manufacturing method of the present invention, and FIGS. 2(a) to 2(d) are process explanatory diagrams of an embodiment of the semiconductor device manufacturing method of the present invention. It is a process explanatory diagram of a method. 21...P-type silicon substrate, 22, 23.28...
Oxide film, 24... Polysilicon film, 25... Phosphorus,
26... Photoresist, 27... Groove, 29... Well. Oni invention's fFX wealth bank monthly map Figure 1 rate exemption of nio! Figure 1 of the construction site is the king of rice! Tomie Ming Ward Map 2

Claims (1)

[Claims] (a) Etching is performed on a first conductive silicon substrate with different etching characteristics from that of silicon.
(b) forming an opening in the first layer; (c) forming a second layer having different etching characteristics from the first layer; (d) forming a sidewall by etching away the second layer leaving only the sidewall of the opening in the first layer; (e) masking the first layer and the sidewall; (f) implanting a third layer having etching characteristics different from that of the second layer and silicon into the opening; (g) using the first layer and the third layer as an etching mask, etching and removing the second layer to form a groove in the silicon substrate; (h) forming a groove in the silicon substrate; A method for manufacturing a semiconductor device, comprising the steps of: forming a fourth layer and filling a trench; and then diffusing a second conductive impurity.