JPH0461163A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need for a high-energy ion implanter by etching a poly-Si film up to the intermediate section of film thickness thereof before impurities are passed through the poly-Si film for ROM coding and implanted to a substrate. CONSTITUTION:A gate oxide film 12 is formed onto a P-type Si substrate 11 through thermal oxidation and B<+> ions are implanted to form a P- channel diffusion layer 13. Poly-Si is deposited on a region 11A, in which a depletion transistor is shaped, and a region 11B, in which an enhancement transistor is formed, phosphorus is doped, and poly-Si films 14A, 14B are formed through patterning. A resist film 15 is formed on the whole surface on the substrate 11, an opening section is shaped to the region 11A and the poly-Si film 14A is exposed, and the poly-Si film 14A is etched to leave film thickness required. P<+> ions are implanted to the substrate 11 while passing through the poly-Si film 14A through the opening section, thus forming an impurity diffusion layer 16. The resist film 15 is removed, and As<+> ions are implanted to the whole surface of the substrate 11, thus shaping a source S and a drain D. Accordingly, manufacturing cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing an N-channel vertical AND type read-only semiconductor memory device. .

(mouth) Conventional technology FIGS. 2 to 4 are explanatory diagrams related to conventional examples.

FIG. 2 is a block diagram of an N-channel vertical AND type read-only semiconductor memory device (NchAND type ROM), and the area surrounded by a broken line circle shows matrix transistors (depression transistors, enhancement transistors).

FIG. 3 shows a conventional non-interrupting transistor (IA) and an enhancement transistor (IB) manufactured in accordance with the prior art.
is a P-type Si substrate, (2) is a selectively oxidized (gate oxidized) Si film, (S) is a source, (G) is a gate, (D>
is dot/in.

Figure 4 shows the RO of the depletion transistor (IA)
It is a process diagram when performing MD-ding.

In the figure, (3) is a resist film, (4) is a P''' channel diffusion layer formed by implanting B+ ions for the enhancement transistor (IB), (5) is a poly-Si film for gate, ( 6) is an impurity that is implanted by ion implantation into the formation region of the poly-Si film (5), the source (S), and the drain (D) for ROM coding of the depletion transistor (IA).
P”).

Note that such prior art includes Japanese Patent Application Laid-Open No. 60-9157 (H (HL 27/10)).

(c) Problems to be Solved by the Invention According to the conventional example, ion implantation for ROM Xi-f implantation of a deep, integrated, single transistor (IA) is performed as shown in FIG. Phosphorus ions are implanted (7) into the P-type Si substrate (1) through the poly-Si film (5).
There must be.

Therefore, an accelerating voltage of about 300 KeV to 400 KeV is required to pass the phosphorus ions through the poly-5i film (5), and this accelerating voltage cannot be obtained with a normal ion implantation device, which is a problem (i). .

The present invention has been made in view of the problems of the conventional example, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables ROM coding using an ion implantation device that normally has a voltage of about 50 KeV to 150 KeV.

(g) Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention is described in the first embodiment.
As shown in Figures A to 1E, a P-type Si substrate (11)
Region where the upper first transistor is formed (], 1.A)
and a gate oxide film (12) is formed in the region (11B) where the second transistor is formed, the region (1, IA) where the first transistor is formed, and the region (1, IA) where the second transistor is formed. IIB>, the gate oxide film (1
2) Selective poly-Si film (14A) (14B>
A resist film (15) is formed on the entire surface of the substrate (11), an opening is provided in the region (11, A) where the first transistor is to be formed, and a poly-Si film (14A) is formed. a step of exposing the poly-Si film (14A) for 6 times; a step of etching the poly-Si film (14A) exposed in the above step to the middle of its film thickness; and a step of implanting phosphorus ions through the opening into the poly-Si film (14A). The substrate (11)
a step of implanting arsenic ions to form an N-type channel impurity diffusion layer (16), and a step of removing the resist film (15) and implanting arsenic ions over the entire surface to form a source (S) and a drain (D). By having this, the above purpose is achieved.

(*) Effect According to the present invention, the first impurity (phosphorus ion) is added to the poly-Si film (
14A) and enter the song into the board (11,),
The method includes a step of etching the poly-Si film (14A) to the middle of its thickness.

This makes it possible to eliminate the need for a conventional high-energy ion implantation device of 3 O0KeV to 40KeV for ROM coding.

(F) Embodiments Next, embodiments of the present invention will be described with reference to the drawings. 1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1A, a region (IIA) where a depletion transistor is to be formed on a P-type Si substrate (11)
and the region where the enhancement transistor is formed (II
B) A gate oxide film of about 300 layers (1
2) and then accelerate the B4' ion with an energy of 7
0KeV, implantation amount I x 10'”1oos/e
Ion implantation is performed under the conditions of nn' to form a P-channel diffusion layer (13).

Next, as shown in FIG. 1B, approximately 4000 0V JSi is applied to the region (IIA) where the depletion transistor is formed and the region (11B) where the enhancement transistor is formed via the gate oxide film (12).
PolySi is deposited by the VD method, doped with phosphorus to lower the resistance, and then patterned to form the gate electrode.
Films (14A) (14B) are formed.

Next, as shown in FIG. 1C, a resist film (15) of about 1.0 μm is formed on the entire surface of the substrate (11),
A photolithography process is performed using a photomask for M coding, an opening is formed in the region (IIA) where the depletion transistor is to be formed, and a poly-Si film (14A) is formed.
expose. Next, the poly-Si film (
14A) was etched for about 1,500 times, leaving a film thickness of about 2,500 times.

, -1 In order to prevent the gate oxide film (12) from being etched at this point, -I, the tweezing Yumata 7 is applied under conditions where the poly(5iO)s twisting speed ratio to Sx, Ot is high.
The etching in step 7 may be anisotropic coating (for example, RiE method) or isotropic etching (dry etching using gas or wet etching using Gothnang liquid).

When using isotropic -1-etching, the controllability of the etching amount is inferior compared to anisotropic etching, but
Since the etching progresses in the lateral direction of the film <14A), the gate length becomes smaller and the depletion transistor (II
There is an advantage that the gm of A) can be improved.

Subsequently, as shown in the first diagram, P" ions are implanted through the opening with an acceleration energy of 80 Kev.
, the substrate (11) was implanted by passing through the poly-Si film (14A) under conditions of 4 x 10" 1 ounces of implantation.
Depletion transistor (IIA)
An N-type channel impurity diffusion layer (16) is formed.

Here, the poly-Si film (14A) has been thinned by an etching process of about 2,500 people, so it has a thickness of 80 Ke.
Depletion transistors can be formed with a low acceleration energy of V, which can be obtained with normal ion implantation equipment, and can be made from 300 KeV to 4 OOKe￥
This eliminates the need for a high-energy ion implanter, reducing manufacturing costs.

Next, as shown in FIG. 1E, the resist film (15) is removed, and As ions are implanted over the entire surface using an ion implantation method at an acceleration energy of 80 KeV and an implantation amount of 5×10”1 ons/e.
rn'' condition into the substrate (11), and the source (S
)・Drain (D) is formed.

Gate (G) here! Poly-Si film (14B>
Since it has a zero thickness of about 4,000 mm, it acts as a protective film against As'' ion implantation, and an enhancement transistor (11B) is formed.

In this way, the depletion transistor (II
A) P” ions are converted to polyS for ROM coding.
Before passing through the i film (14A) and implanting it into the substrate (11), the tZ IJ Si! (14A) 2500
Since the coating is applied to a film thickness of about A, the acceleration energy is 8°Ke which can be obtained with a normal ion implanter.
About V is sufficient.

Therefore, it becomes possible to eliminate the need for a conventional ion implantation device with high acceleration energy.

(g) As described in detail, according to the present invention, the ROM coding of the deep-transistor transistor can be performed using a normal ion implantation device (acceleration energy: about 50 KeV to 150 KeV).
Therefore, it is possible to reduce the manufacturing cost of the semiconductor device and speed up the processing process.

[Brief explanation of drawings]

1A to 1E are sectional views for explaining the method of manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 4 are explanatory views for a conventional example.

Claims (2)

[Claims] (1) A step of forming a gate oxide film in a region where a first transistor is to be formed and a region where a second transistor is to be formed on a semiconductor substrate of one conductivity type; selectively forming a polycrystalline semiconductor film through the gate oxide film in a region where a first transistor is to be formed; forming a resist film over the entire surface of the substrate, and forming an opening in a region where a first transistor is to be formed; a step of etching the polycrystalline semiconductor film exposed in the step to the middle of its film thickness; and a step of etching the polycrystalline semiconductor film exposed in the step to the middle of its thickness; is implanted into the substrate through the polycrystalline semiconductor film using an ion implantation method to form a channel impurity diffusion layer of an opposite conductivity type; removing the resist film and implanting a second impurity into the entire surface; 1. A method of manufacturing a semiconductor device, comprising the step of forming a source and a drain. (2) The semiconductor device according to claim 1, wherein the first transistor is a depletion transistor, the second transistor is an enhancement transistor, and the first and second impurities are phosphorus ions and arsenic ions. How to make