JPH0456268A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the obstruction to the micronization due to a margin between a contact hole and an isolating region not to be taken into consideration by a method wherein the contact hole of a first diffusion region is expanded up to the isolating region. CONSTITUTION:A trench 3 is formed including an N<+>-type first diffusion layer region 2, a P<->-type channel stopper 5 is formed, an oxide film 7 is deposited, a first nitride film 8 is provided, and the first nitride film 8 is left unremoved only on the side wall of the trench 3. Then, a second selective oxide film 9 and a second nitride film 10 are deposited on the base of the trench 3, the second nitride film 10 formed on the base of the trench 3 is removed through anisotropic etching, the inside of the trench 3 is filled with a buried oxide film 11, then an etching mask 12 is formed, the first nitride film 8 and the second nitride film 10 are removed through anisotropic etching, the oxide film 7 on the side wall is removed through etching, and an N<+>-type second diffusion layer region 13 is formed. A buried polycrystalline silicon electrode 14 is formed inside the trench 3, an interlaminar insulating film 15 is deposited, and then a contact hole 16 is buried.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.

Conventional technology Conventionally, when forming a contact to the source or drain of a MOS transistor formed on a silicon substrate, contact holes are formed in the source diffusion region and drain diffusion region using photolithography on the surface of the silicon substrate. is common.

A conventional method for manufacturing a semiconductor device will be described below.

Figure 3 shows the source diffusion region of a MOS transistor.

FIG. 3 is a plan view for explaining a method of forming a contact in a drain diffusion region. As shown in the figure, in the conventional contact forming method, a contact hole 16 is formed in the source or drain diffusion region 2. 1 is a gate region.

Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, although elements are becoming finer as photolithography technology progresses, margins for forming isolation regions between transistors and contact holes in source diffusion regions or drain diffusion regions are insufficient. This has become a limit to the miniaturization of the entire integrated circuit.

The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that does not require consideration of the margin between a contact hole and an isolation region.

Means for Solving the Problems In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes forming a contact hole in a source diffusion region or a drain diffusion region (hereinafter collectively referred to as a first diffusion layer region). In order to do this, a trench is formed including an isolation region and a contact hole, a silicon oxide pillar is formed inside the trench, and then ions are implanted into the sidewalls of the trench to form a trench connected to the first diffusion layer region. A second diffusion layer region is formed, a polycrystalline silicon electrode is buried between the silicon oxide pillar and the trench sidewall, and a contact hole containing polycrystalline silicon is formed in the first diffusion layer region.

Effect: With this configuration, the contact hole in the first diffusion layer region can be extended to the isolation region (in the present invention, element isolation is performed at the bottom of the trench), and the margin between the contact hole and the isolation region allows for miniaturization. There is no need to consider obstacles.

Further, when ion implantation is performed inside the trench, a p-type diffusion layer and an n-type diffusion layer necessary for forming an element can be formed at the same time.

EXAMPLE An example of the present invention will be described below with reference to FIG.

FIG. 1(a) is a plan view showing the main parts of two MOS transistors, and FIG. 1(b) to (i) are sectional views in the order of steps.

In the figure, 1 is a gate region, 2 is an n1 type first diffusion layer region such as a source diffusion region or a drain diffusion region,
Region 3 surrounded by a broken line is a trench region.

First, a resist film is formed in a region other than the trench region 3, and the oxide film 4 is etched using the resist film as a mask. Then, silicon is etched using the oxide film 4 as a mask. FIG. 5B is a cross-sectional view taken along line AA' (in the direction of the expansion layer region) of FIG. A trench 3 is formed including a first extension layer region 2 of n+ type. 4
is an oxide film. Figure (e) is a sectional view taken along line BB' (separation region direction) of figure (a). As shown in these figures, boron ions (B+) are implanted into the sidewalls and bottom of trench 3 using a large tilt ion implanter at approximately 2X
About 10 I3cwl-2 is injected, and a p-type channel stopper 5 is formed there. 6 is a first selective oxide film.

Next, as shown in FIG. 1(ω) (cross-sectional view taken along line A-A' in FIG. 1(a)), a thin oxide film 7 of about 500A is formed inside the trench 3, and then a low pressure CVD method ( LPCVD
A first nitride film 8 is deposited to a thickness of about 1500 Å using a method (method).

Then, the nitride film at the bottom of the trench 3 is removed by anisotropic dry etching, leaving the first nitride film 8 only on the side walls of the trench 3. Next, as shown in FIG. 1(e), a second selective oxide film 9 is formed at the bottom of the trench 3. Thereafter, a second nitride film 10 is deposited, and the second nitride film 10 at the bottom of the trench 3 is removed by anisotropic etching. After filling the inside of the trench 3 with a buried oxide film 11,
A resist film is applied to the entire surface to form an etching mask 12. Here, Fig. 1(e) corresponds to a cross-sectional view taken along line A-A' in Fig. 1(a), and figure (f) corresponds to a cross-sectional view taken along line B-B'. It is. First nitride film 8 in isolation region direction (BB') using resist mask 12
Then, the second nitride film 10 is removed by anisotropic dry etching. Thereafter, the first nitride film 8 and the second nitride film 10 remaining inside the trench 3 are removed by etching. This state is shown in Figure 1(g) (A-A in Figure 1(a)).
This is a cross-sectional view taken along the line ' (h) and (i) below.

That is, a column of buried oxide film 11 stands at the center of trench 3. Next, after removing the thin oxide film 7 on the side wall of the trench 3 by etching, approximately 50% of arsenic ions (As+) are injected into the side wall of the trench 3 in the direction of the diffusion layer region (A-A'M) using a large tilt ion implanter. Inject about ×10”ell-2,
An n medium-sized second diffusion layer region 13 is formed. In addition, when forming a contact when the n-type and p-type are open, one of the side walls of the trench 3 in the direction of the diffusion layer region (AA') is made of As+
An n+ type diffusion layer region is formed on the other side, and BF is formed on the other side.
By implanting approximately 3×10"c+a-2 of 2+ to form a p+ type diffusion layer region, it is possible to simultaneously form p-type and n-type contacts within one trench. As shown in Figure 1 (噸), the low pressure CVD method (
Polycrystalline silicon is buried inside the trench 3 using the LPCVD method to form a buried polycrystalline silicon electrode 14. Finally, as shown in FIG. 1(i), the interlayer insulating film 15
After depositing, a contact hole 16 is formed so as to span the buried polycrystalline silicon electrode 14.

Incidentally, the relationship between the masks in the implementation row of the present invention is shown in the second section. As shown in the figure, the contact hole 16 is formed so as to extend over both the first diffusion layer region 2 and the trench 3, and the first diffusion layer region 2 extending outward from the gate region 1 is formed in a conventional manner as shown in FIG. Compared to the conventional method, the margin between the isolation region and the contact hole can be reduced by 0.2 μm, and the polycrystalline silicon formed on the isolation region can be By forming a contact to the electrode, the margin is reduced to 0.3μ.
m can be reduced, and the element spacing can be reduced by a total of about 0.5 μm (on one side).

Effects of the Invention As described above, the present invention eliminates the need to consider the margin between the contact hole and the element isolation region, and allows the formation of a contact hole that spans the buried polycrystalline silicon electrode on the element isolation region, thereby facilitating miniaturization of elements. I can do it. 1 more
N-type and p-type contacts can be formed simultaneously in a single trench.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a semiconductor device according to the manufacturing method of the present invention, FIGS. 1(b) to (i) are sectional views in the same process order, and FIG. FIG. 3 is a plan view showing the relationship between masks in a conventional semiconductor device manufacturing method. 2...First diffusion layer region (source diffusion region, drain diffusion region), 3...Trench, 11...
...Buried oxide film, 13...Second diffusion layer region (diffusion layer), 14...Buried polycrystalline silicon electrode (polycrystalline silicon electrode), 15... ...Interlayer insulating film, 16...Contact hole. Name of agent: Patent attorney Shigetaka Awano and one other person not shown.

Claims (2)

[Claims] (1) Part of the source diffusion region of the first MOS transistor and the drain diffusion region of the second MOS transistor formed in the semiconductor substrate, part of the isolation region of the first and second MOS transistors, and the first and second MOS transistors. a step of forming a trench including a part of the isolation region of the second MOS transistor; a step of forming a pillar of a buried oxide film having a space between the trench sidewall and the trench sidewall; A step of forming a diffusion layer connected to a source diffusion region or a drain diffusion region, a step of embedding a polycrystalline silicon electrode between the column of the buried oxide film and the side wall of the trench, and an interlayer insulating film formed on the entire surface of the semiconductor substrate. and forming contact holes for source and drain diffusion regions including part of the polycrystalline silicon electrode in the interlayer insulating film. (2) The method for manufacturing a semiconductor device according to claim 1, wherein one of the first MOS transistor and the second MOS transistor is an n-type, and the other is a p-type.