JPH09134954A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the edge part in an element isolating area from being etched, by making the film consisting of a second insulating matter have a function as an etching stopper in forming contact hole. SOLUTION: A semiconductor substrate 101 is provided with a groove 105, and this is charged with a silicon oxide film 106, and it is polished to form a buried element isolating area 107. Next, the silicon oxide film on the surface of the buried element isolating area 107 is removed, using ammonium fluoride etching, so as to retreat the edge part in the buried element area. Next, a silicon oxide film such as, for example, a silicon nitride film, and a film 108 having etching selectivity are stacked by for example 10nm. Next, a silicon nitride sidewall 109 is made at the section where the edge has retreated of the buried element isolating region 107, using anisotropic etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device and a cell array of a memory LSI.

[0002]

2. Description of the Related Art With the miniaturization of memory cell arrays of LSIs, the area of SDG regions has been reduced, and it has become difficult to provide a sufficient alignment margin with these SDG regions in the contact formation process. Therefore, misalignment between the SDG region and the contact hole due to patterning may occur, the contact hole may be displaced from the SDG region, and may reach the element isolation region.

Further, in the lithography technique, the miniaturization of the contact hole is more sophisticated than the miniaturization of the pattern width. For this reason, when the minimum patternable size is applied to each, the diameter of the contact hole becomes larger than the SDG width, and even if there is no misalignment in contact formation, the contact hole is formed in the element isolation region. May be affected.

A cross-sectional view of a conventional semiconductor device is shown in FIG.
As shown in FIG. 3A, an element isolation region 302 and an SDG region 303 are formed at arbitrary places on the silicon substrate 301. An impurity diffusion layer 304 is formed in the SDG region 303 by ion implantation. An interlayer oxide film 305 is deposited on the entire surface of the silicon substrate and etched by a lithography method to form a contact hole 306 for wiring. Further, the wiring layer 307 is formed by depositing the material forming the wiring layer.

If misalignment of the mask occurs when the contact hole is formed by the lithography method, as shown in FIG.
As shown in (b), the insulating film at the edge of the element isolation region 302 is etched, and the silicon substrate 301 is exposed. For this reason, the wiring layer 308 comes into contact with the silicon substrate 301 at a portion which is not covered with the impurity diffusion layer 304 formed in the SDG region, and the wiring layer 307 and the silicon substrate 301 are short-circuited.

On the other hand, after the contact opening, ion implantation is performed again to form the impurity diffusion layer 309, and the silicon substrate 301 and the wiring layer 308 due to the displacement of the contact hole.
The method of preventing the short-circuiting phenomenon is used.

As described above, when the element isolation region is formed by the LOCOS method, since the insulating film at the edge portion (bird's beak) is thin, the exposed silicon substrate surface does not have a large step with respect to the surface of the SDG formation region. For this reason,
It is possible to perform ion implantation after the contact opening and re-diffuse impurities into the exposed silicon substrate.

Next, a method of manufacturing a semiconductor device in the case of forming an element isolation region by a buried element isolation method will be described with reference to FIGS. As shown in FIG. 4A, a silicon oxide film 402 is formed on the semiconductor substrate 401 by, for example, 25 nm.
Then, a polycrystalline silicon 403 is formed, for example, 400
nm. Then, a resist pattern 404 is formed.

Next, as shown in FIG. 4B, the polycrystalline silicon 403, the silicon oxide film 402, and the semiconductor substrate 401 are etched by a lithography method to form a trench 405.

Next, as shown in FIG. 4C, the resist pattern 404 is removed, and a silicon oxide film 406 is deposited to a thickness of 1000 nm, for example, by a vapor phase epitaxy method to fill the trench 405. Then, as shown in FIG.
The silicon oxide film 406 and the polycrystalline silicon 40 are polished.
Remove part of 3. The polycrystalline silicon 403 functions as a stopper material when polishing the silicon oxide film 406.

Next, as shown in FIG. 5A, the polycrystalline silicon 403 is entirely etched by, for example, isotropic etching, and the silicon oxide film 402 is removed by, for example, ammonium fluoride etching. The silicon oxide film 402 is provided so that the semiconductor substrate 401 is not etched when the polycrystalline silicon 403 is removed. By the etching for removing the silicon oxide film 402,
The surface of the silicon oxide film 406 filled in the groove 405 may recede. After that, as shown in FIG.
An N-type impurity is added to the semiconductor substrate 401 by an ion implantation method, and thermal diffusion is performed to form an impurity diffusion region 407.

Next, as shown in FIG. 5C, an inter-layer insulating film 408 is deposited to a thickness of 400 nm, for example, and the inter-layer insulating film 408 in the contact formation planned portion of the impurity diffusion region 407 is removed by etching using a lithography method. As shown in FIG. 5D, contact holes 409 are formed. Further, by depositing the material forming the wiring layer, the wiring layer 410 is formed as shown in FIG.

If misalignment of the mask occurs during formation of the contact hole by the lithography method, the interlayer insulating film 40 is formed.
When 8 is etched, as shown in FIG. 5F, a part of the silicon oxide film 406 forming the element isolation region is removed and a groove 412 is formed in the contact hole 411. After that, since the wiring layer 413 is formed in the contact hole 411, the wiring layer 413 comes into contact with the silicon substrate 401 at a portion not covered with the impurity diffusion region 407,
As shown in FIG. 5G, the wiring layer 413 and the silicon substrate 401 are short-circuited.

When the element isolation region is formed by the buried element isolation method, since the insulating film 306 is deeply buried, the groove 412 of the contact hole is deeply etched due to the mask shift. This groove 412 becomes deeper as the taper angle of the element isolation trench and the taper angle of contact etching are larger and the width of the contact in the element isolation region is larger. As a measure against short circuit between the wiring layer and the semiconductor substrate, the method of re-diffusing impurities after the contact opening used when forming the element isolation region by the LOCOS method is difficult to ion-implant into a narrow and deep groove. Therefore, it cannot be applied.

[0015]

In the semiconductor device using the buried element isolation method as described above, when the lithography method is used when forming the contact hole, the edge portion of the element isolation region is generated when a mask shift occurs. However, when a wiring layer is formed in this contact hole, a phenomenon such as a short circuit between the wiring layer and the semiconductor substrate and a problem such as a junction leak occur. The present invention has been made in view of the above-mentioned drawbacks, and in a contact hole extending over a buried element isolation region, a semiconductor device having an etching stopper that prevents etching of an edge portion of the buried element isolation region that occurs at the time of the opening, and a method for manufacturing the same. It is provided.

[0016]

According to the present invention, an element isolation region is formed by filling a groove provided in a semiconductor substrate with a first insulating material, and an edge portion above the element isolation region. A film portion made of a second insulating material, and an interlayer insulating film made of a third insulating material having etching selectivity with the second insulating material formed on the semiconductor substrate,
The present invention provides a semiconductor device and a method for manufacturing the same, wherein the film portion made of the second insulating material has a function as an etching stopper when forming a contact hole.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing method of the present invention will be described as a first embodiment with reference to FIG. First, as shown in FIG. 1A, in a semiconductor device manufacturing method using a conventional buried element isolation method (see FIG. 4), a semiconductor substrate 101 and a groove 105 (conventional example 405 are formed). (Equivalent) is provided, and the silicon oxide film 106 is
(Corresponding to 606 in the conventional example) is filled and the surface is polished to form the buried element isolation region 107. At this time,
The element isolation region 107 is assumed to project from the surface of the semiconductor substrate 101.

Next, as shown in FIG. 1B, the silicon oxide film on the surface of the buried element isolation region 107 is removed by using, for example, ammonium fluoride etching (NH4F), and the edge portion of the buried element isolation region is removed. Retreat.
This step can also serve as a step of removing the silicon oxide film (corresponding to 402 of the conventional example) formed as an etching stopper when etching the groove 105. It may also serve as the step of removing the dummy gate oxide film when the MOSFET is formed.

Next, as shown in FIG. 1C, a film 108 having etching selectivity with respect to the silicon oxide film, such as a silicon nitride film, is deposited to a thickness of 100 nm, for example. Next, as shown in FIG. 1D, a silicon nitride film side wall 109 is formed on the recessed portion of the buried element isolation region 107 by anisotropic etching. This step can be combined with the LDD side wall forming step when the MOSFET is formed. After that, an impurity such as As is added to the semiconductor substrate 101 by an ion implantation method at a dose of 3 × 10 15 at an acceleration of 40 kev,
Then, impurity diffusion and damage recovery are performed by, for example, heat treatment at 850 ° C. for 10 minutes in an N 2 atmosphere to form an impurity diffusion region 110.

Next, as shown in FIG. 1E, an interlayer insulating film 111 is deposited to a thickness of 400 nm, for example, and the interlayer insulating film 111 in the contact formation planned portion of the impurity diffusion region 110 is removed by etching using a lithography method. As shown in FIG. 1F, the contact hole 112 is formed. afterwards,
In this contact hole 112, as shown in FIG.
The wiring layer 113 is formed.

Even if the mask is misaligned when the contact hole is formed by the lithography method, and the etching is applied to the element isolation region 107 as shown in FIG. Since the silicon nitride film 109 formed in the recessed portion of the edge of the isolation region acts as an etching stopper,
The element isolation region 107 is not dug. Then, FIG.
As shown in (g), the wiring layer 11 is formed in the contact hole 112.
3 is formed, the wiring layer 113 comes into contact with the silicon substrate only in the impurity diffusion region 110 that is the contact formation planned region, and the wiring layer 113 and the silicon substrate 10 are connected.
1 short circuit can be prevented.

As a second embodiment, a case where the step difference between the silicon substrate and the embedded element region is small will be described. When the remaining film thickness after polishing of the polycrystalline silicon used as the stopper material when polishing the silicon oxide film filled in the groove when forming the buried element isolation region is thin, or when the stopper layer can be thinned Moreover, such a structure can be obtained.

First, the procedure up to the step of forming the element isolation region is the same as in the conventional example and the first embodiment. In this case, as shown in FIG. 2A, the element isolation region 202 has a small step with the silicon substrate 201, and the protruding portion is considerably smaller than in the case of the first embodiment described above.

Next, as shown in FIG. 2B, the silicon oxide film on the surface of the buried element isolation region 202 is removed using, for example, ammonium fluoride etching (NH4F), and the edge portion of the buried element isolation region is removed. Retreat.
In this case, the edge portion of the element isolation region 202 is etched deeper than the surface of the silicon substrate 201.

Next, as shown in FIG. 2C, for example, a silicon nitride film 203 is deposited. Next, as shown in FIG. 2D, a silicon nitride film side wall 204 is formed on the recessed portion of the buried element isolation region 202 by anisotropic etching. After that, an impurity is added to the semiconductor substrate 201 by an ion implantation method, and then impurity diffusion is performed by heat treatment to perform damage recovery and an impurity diffusion layer 205 is formed.

Next, as shown in FIG. 2E, an inter-layer insulating film 206 is deposited, and the inter-layer insulating film 206 in the contact formation planned portion of the impurity diffusion layer 205 is formed by using a lithography method.
Are removed by etching to form a contact hole 207.
Thereafter, a wiring layer 208 is formed in the contact hole 207, as shown in FIG.

If a mask misalignment occurs during the formation of the contact hole by the lithography method, the interlayer insulating film 20 is formed.
2G, the silicon nitride film 204 formed in the recessed portion of the edge of the element isolation region acts as an etching stopper even if the element isolation region 202 is etched as shown in FIG. Therefore, the substrate is not dug into the silicon substrate 201. Next, as shown in FIG. 2H, since the wiring layer 208 is formed in the contact hole 207, the wiring layer 208 comes into contact with the silicon substrate only in the impurity diffusion region 205, which is the region where the contact is to be formed. A short circuit between the layer 208 and the silicon substrate 201 can be prevented.

[0028]

According to the semiconductor device of the present invention, when a contact hole is formed in the semiconductor device using the buried element isolation method, the edge portion of the element isolation region which is in contact with the SDG region of the element isolation region is selected by oxide film etching. By providing a film having properties and functioning as an etching stopper, it is possible to prevent the edge portion of the element isolation region from being etched when the oxide film is etched at the time of contact opening,
The contact between the wiring layer formed in the contact hole and the silicon substrate is avoided. For this reason, it becomes possible to avoid a junction leak due to the digging of the edge of the buried element isolation region. In the semiconductor device of the present invention, S
Since the contact alignment margin in the DG region can be reduced, the semiconductor device can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device having an element isolation region using a conventional LOCOS method.

FIG. 4 is a cross-sectional view showing a step of forming a conventional buried element isolation region.

FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device having a conventional buried element isolation region.

[Explanation of symbols]

 101 semiconductor substrate 107 element isolation region 108 silicon nitride film 109 film portion of silicon nitride film 110 impurity diffusion region 111 interlayer insulating film 112 contact hole 113 wiring layer 114 contact hole 115 wiring layer 201 semiconductor substrate 202 element isolation region 203 silicon nitride film 204 Film portion of silicon nitride film 205 Impurity diffusion region 207 Contact hole 208 Wiring layer 301 Silicon substrate 302 Element isolation region 304 Impurity diffusion region 307 Wiring layer 308 Wiring layer 309 Second impurity diffusion layer 401 Semiconductor substrate 402 Silicon oxide film 403 Polycrystal Silicon 404 Resist pattern 406 Element isolation region 407 Impurity diffusion layer 409 Contact hole 410 Wiring layer 411 Contact hole 412 Digging element isolation region 413 Wiring layer

Claims (5)

[Claims] 1. An element isolation region formed by filling a groove provided in a semiconductor substrate with a first insulating material, and a second insulating material formed at an edge portion above the element isolation region. A film portion and an interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film including a second insulating material and a third insulating material having an etching selectivity, and the film portion including the second insulating material is a contact. A semiconductor device having a function as an etching stopper when forming a hole. 2. The bottom surface of the film portion made of the second insulating material is higher than the surface of the semiconductor substrate.
13. The semiconductor device according to claim 1. 3. The bottom surface of the film portion made of the second insulating material is lower than the surface of the semiconductor substrate.
13. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein a silicon oxide film is used as the first insulating material, and a silicon nitride film is used as the second insulating material. 5. A step of forming a buried element isolation region made of a first insulating material on a semiconductor substrate, a step of removing an upper surface of the buried element isolation region by isotropic etching, and retreating an edge portion thereof. A step of depositing a film made of a second insulating material on the semiconductor substrate; and anisotropically etching the film made of the second insulating material so that the edge portion of the upper surface of the buried element isolation region has A step of forming a film portion made of a second insulating material; and a step of forming an interlayer insulating film made of a third insulating material having etching selectivity with the second insulating material on the entire surface of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein the film portion made of the second insulating material has a function as an etching stopper during etching for forming the contact hole.