JPS62272332A - Tracer system - Google Patents

Abstract

PURPOSE:To efficiently use a memory by providing plural memories and storing macro instruction addresses in the same prescribed address of a memory and storing information indicating the change of the macro instruction address in another memory together with the micro instruction address for the change when the same macro instruction address continues. CONSTITUTION:Plural memories are provided, and macro instruction addresses and micro instruction addresses are stored in memories 1 and 2 independent of each other. if the same macro instruction address continues, this macro instruction address is stored over in the same address of the memory 1. Thus, macro instruction addresses for a time considerably longer than that in the conventional tracer system are stored. A bit indicating the change of the macro instruction address is inputted to the memory 2 together with the micro instruction address for the change to allow macro instruction addresses inputted to the memory 1 and micro instruction address inputted to the memory 2 to correspond to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention 1 Hill 11 The present invention relates to a tracer method, and particularly to a tracer method for storing a fat layer of an internal state of an information processing device.

Prior Art Conventionally, in this type of tracer method, a tracer circuit composed of a memory, an address circuit, and a control circuit constantly writes data indicating the internal state of an information processing device to the memory while changing the write address. There is. When data is written to all words of this memory, the write address is returned to the initial address and is written over the previously written word.

This operation continues until the information processing device detects a failure. When a fault is detected, the tracer circuit stops updating the write address and writing to the memory via the control circuit,
Data indicating the internal state of the information processing device is stored in the memory with the maximum number of words in the memory going back from the failure detection.

Since such a conventional tracer system has only one memory, data that change over different periods, that is, macroinstruction addresses and microinstruction addresses, are simultaneously input into the same memory. Generally, this microinstruction address changes every clock, whereas the macroinstruction address usually does not change for several to several tens of clocks. Therefore, since the same address is input to multiple words on the memory in the case of a macro instruction address, there is a drawback that the part of the memory where the macro instruction address is input is not used effectively.

OBJECTS OF THE INVENTION The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional methods, and an object of the present invention is to provide a tracer method that can use memory efficiently.

Structure of the Invention The tracer method according to the present invention is a trainer method that stores data indicating the internal state of an information processing device, and is provided with a plurality of memories, and when macro instruction addresses from the information processing device are consecutive at the same address. , the macro instruction address is stored at a predetermined same address in the memory, and information indicating a change in the macro instruction address is stored in another memory together with the micro instruction address at the time of the change. Features.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the tracer circuit according to one embodiment of the present invention includes a memory 1.2, a data register 3, a comparison circuit 4, a state holding circuit 5, an address counter circuit 6.7, and a control circuit 8. has been done.

FIG. 2 is a more detailed circuit diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. The configuration and operation of an embodiment of the present invention will be explained in detail using FIG. 1 and FIG. 2.

The memory 1 has a bit width sufficient to store a macro instruction address for accessing a main memory (not shown) in which a macro program is stored, and a sufficient number of words to store a macro instruction address when a failure occurs. This macro instruction address is written into the word specified by the address output by the address counter circuit 6 when the control circuit 8 instructs it with the write instruction signal.

The memory 2 stores a microinstruction address for accessing a control memory (not shown) storing a microprogram, data indicating the state of an information processing device (not shown) containing this control memory, and a mismatch signal. It also has a sufficient number of words to store these addresses, data, and signals in the event of a failure.

These addresses, data, and signals are written into the memory 2 in the word specified by the address output from the address counter circuit 7 when the control circuit 8 instructs it with a write instruction signal.

The data register 3 inputs and holds the macro instruction address input to the memory 1. The macro instruction address held in the data register 3 is sent to the comparison circuit 4.

The comparison circuit 4 is composed of a comparator 40, which receives the macro instruction address input to the memory 1 and the macro instruction address held in the data register 3, compares these addresses, and determines if these addresses do not match. Outputs a no-togi mismatch signal.

This mismatch signal is input to the memory 2 together with the microinstruction address at that time as a signal indicating that the macroinstruction address has changed, and the correspondence between the macroinstruction address and the microinstruction address is established. and is used as one of the conditions for updating the write address of the address counter circuit 6.

The state holding circuit 5 includes a register 50 and three AND circuits 5.
1, register 52, OR circuit 53, and NOT circuit 5
4. The register 50 stores and holds mask data specifying valid conditions among the stop conditions. This mask data is given externally,
It is stored in the register 50 by a mask set signal from the outside.

The AND circuit 51 ANDs the 3-bit output of the register 50 and the stop condition specified by each bit and outputs a stop signal. For this stop condition, detection signals of various failures within the information processing device are used. The register 52 inputs the stop signal from the AND circuit 51, stores and holds this stop signal, and is reset by an external operation start signal to initialize the held stop signal.

The OR circuit 53 receives the 3-bit stop signal of the register 52,
OR with the external forced stop signal.

Both of these signals indicate that writing of data to memory 1.2 is stopped. NOT circuit 54 inverts the output from OR circuit 53 and outputs a signal indicating that data writing to memory 1.2 is active. This signal is used as one of the update conditions for the write address of the address counter circuit 6, or as one of the update conditions for the write address of the address counter circuit 7, or
It is used as a write instruction signal for memories 1 and 2.

Further, this signal is used as a set signal to set a stop signal in the register 52.

The address counter circuit 6 includes a register 60 and a +17 register 6.
1, an adder 62, and a switch 63, and a register 60 and a +17 adder 61 form a counter for creating a write address of the memory 1. The +17 der 61 inputs all bits of the register 60, adds +1 to the input contents, and returns the result to the register 60. The register 60 uses the signal from the control circuit 8 as a set signal to set the output from the +17 der 61. Roughly, the register 60 outputs its contents to the adder 62 and the switch 63.

The adder 62 inputs the write address of the register 60 and external subtraction data, subtracts the subtraction data from this write address, outputs the subtraction result, and uses the fixed write address as a read address for memory 1. used to create relative addresses. The switch 63 switches between the write address of the register 60 and the read address output from the adder 62 based on the output signal from the state holding circuit 5. When this output signal is "1", that is, when writing data to the memories 1 and 2 is in operation, the switch 63 selects the write address of the register 60. When this output signal is "0", that is, when writing of data to the memory 1.2 is stopped due to occurrence of a failure or the like, the switch 63 selects the read address of the adder 62.

The address counter circuit 7 includes a register 70 and a +17 der 7.
1, an adder 72, and a switch 73, and a register 70 and a +17 adder 71 form a counter for creating a write address of the memory 2. The +17der 71 inputs all the pits of the register 70, adds +1 to this input content, and returns it to the register 70. The register 70 outputs the output signal from the +17der 71 using the output signal "1" of the state holding circuit 5 as a set signal. Set. Furthermore, the register 70 outputs the contents to the adder 72 and the switch 173.

The adder 72 inputs the write address of the register 70 and the subtraction data from the outside, subtracts the subtraction data from this write address, outputs the subtraction result, and uses the fixed write address as the read address for the memory 2. Used to create relative addresses from. Switching 2S73
switches between the write address of the register 70 and the read address output from the adder 72 by the output signal from the state holding circuit 5. When this output signal is "1", the switch 73 selects the write address of the register 70, and when this output signal is "0", it selects the read address of the adder 72.

The control circuit 8 is composed of an AND circuit 80. The AND circuit 80 ANDs the mismatch signal from the comparator circuit 4 and the signal from the state holding circuit 5 to ensure that the data can be written to the memory 1.2 and the macro command that was previously input to the memory 1. A signal indicating that the address and the currently input macro command address do not match is generated, and the write address of the address counter circuit 6 is updated by this signal.

When the mismatch signal from the comparator circuit 4 is rOJ, that is, when the macro instruction addresses are the same and consecutive, the write address of the address counter circuit 6 is not updated and the macro instruction address is written to the same address in the memory 1. . This means that the mismatch signal from the comparison circuit 4 is [1
] is repeated until

In this way, a plurality of memories are provided so that macro instruction addresses and micro instruction addresses are stored in separate memories 1 and 2, respectively, and when macro instruction addresses are consecutive at the same address, they are stored at the same address in memory 1. By storing these macroinstruction addresses in an overlapping manner, it is possible to store macroinstruction addresses for a much longer period of time than in the conventional tracer method. In addition, by inputting a bit indicating that the macro instruction address has changed into the same memory together with the micro instruction address at the time of the change, the macro instruction address and micro instruction address input into separate memories can be correlated. Can be done.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a plurality of memories are provided, macro instruction addresses and micro instruction addresses are stored in separate memories, and when the macro instruction addresses are the same address and are related, Memory is used efficiently by overlapping and storing this macro instruction address at the same address in memory and storing the bit indicating that the macro instruction address has changed together with the micro instruction address at the time of the change. It has the effect of being able to

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a more detailed circuit diagram showing one embodiment of the present invention. Explanation of symbols of main parts 1.2...Memory 3...Data register 4...Comparison circuit 6.7...Address counter circuit 8...・・・
・t, II control circuit

Claims (1)

[Claims] A tracer method for storing data indicating the internal state of an information processing device, in which a plurality of memories are provided, and when macro instruction addresses from the information processing device are consecutive at the same address, the macro instruction address is stored in one of the memories. A tracer method characterized in that information indicating a change in the macroinstruction address is stored in another of the memories together with the microinstruction address at the time of the change.