JPH07281917A - Cpu switchin circuit - Google Patents

Abstract

PURPOSE:To enable a stand-by system to perform the processing different from that of an active system in a normal operation mode and to attain the memory succession processing without control of the CPUs, the firmware, etc. CONSTITUTION:When a selection signal 122 is inputted, a pulse generating circuit 3 outputs the same address signals 131 to the memory circuits 1 and 2 and then outputs a read signal 133 and a write signal 133 to the circuits 1 and 2 respectively. The information read out of the circuit 1 is immediately written in an address of the circuit 2 which is equal to the address of the circuit 1. Then the circuit 3 repeats the read/write control operations in frequency equal to that of the counter value 121 and outputs a switch permission signal 134 when all information are read out of the circuit 1 and written in the circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU switching circuit,
In particular, the present invention relates to a CPU switching system for a system having a redundant configuration with active and standby CPUs.

[0002]

2. Description of the Related Art Conventionally, in a system having a redundant configuration of this type, a hot standby system that causes an active CPU and a standby CPU to perform the same processing respectively, and a standby system when the active CPU is operating. There is a cold standby system that does not operate any of the CPUs.

In a cold standby system, when switching from the active CPU to the standby CPU, the active CP
The contents of the memory used by U must be inherited by the memory used by the standby CPU.

That is, as shown in FIG. 3, the switching control circuit (CPU) 6 switches the switching signal (SEL) 222 when switching from the active CPU (not shown) to the standby CPU (not shown).
Is input, control is performed to read the contents from the memory circuit 4 used by the active CPU (hereinafter referred to as the active memory circuit).

The data read from the active system memory circuit 4 under the control of the switching control circuit 6 is saved in the shared memory circuit 7 under the control of the switching control circuit 6 and then used by the standby system CPU from the shared memory circuit 7. Memory circuit 5 (hereinafter,
It is copied to the standby memory circuit).

An address signal (ADD) 201 and a write signal (WR) are sent from the active CPU to the active memory circuit 4.
203 and a read signal (RD) 204 are input, and the data signal (DATA) 202 is exchanged with the active CPU.

Further, the switching control circuit 6 sends an address signal (ADD) 231 and a read signal (R) to the active memory circuit 4.
D) 233 and the address signal (ADD) 231 and the write signal (WR) 233 from the switching control circuit 6 to the shared memory circuit 7, the active memory circuit 4
Data signal (DATA) 2 between the shared memory circuit 7 and the shared memory circuit 7.
32 transfers are made.

On the other hand, the standby system memory circuit 5 has a standby system C
An address signal (ADD) 211, a write signal (WR) 213, and a read signal (RD) 214 are input from the PU, and a data signal (DATA) 2 is input to and from the standby CPU.
Give and receive twelve.

Further, the shared memory circuit 7 includes a switching control circuit 6
Address signal (ADD) 231 and read signal (R
D) 235 and the address signal (ADD) 231 and the read signal (WR) 235 from the switching control circuit 6 to the standby system memory circuit 5, the standby system memory circuit 5 and the shared memory circuit 7 are connected. Data signal between (DATA)
234 is exchanged.

As a result, the environment of the active CPU and the environment of the standby CPU become the same, so that the CP of the standby system
When U switches to the active system and operates, the CP of the standby system
In U, the operation of the active CPU before switching is guaranteed.

[0011]

In the conventional system described above, in the case of a hot standby system, the standby CPU must perform the same processing as the active CPU during normal operation, so that the system efficiency is improved. Becomes worse.

Further, in the case of a cold standby system, when switching from the standby system to the active system, it is necessary to make the standby system memory inherit the contents of the active system memory. circuit)
Or firmware is needed.

Therefore, an object of the present invention is to solve the above-mentioned problems and to make the CPU of the active system a CPU of the standby system during normal operation.
It is an object of the present invention to provide a CPU switching circuit that can perform a process different from that of a PU and that can perform a memory inheritance process without control of a CPU, firmware, and the like.

[0014]

A CPU switching circuit according to the present invention includes first and second central processing units, and
Is a CPU switching circuit of an information processing system that uses the second central processing unit as a standby system when the central processing unit is used as an active system, and a switching instruction for switching from the standby system to the active system. A second memory which is responsive to a signal to read the contents of a first memory device uniquely used by said first central processing unit and whose read contents are uniquely used by said second central processing unit. Means for simultaneously writing to the device and switching from the first central processing unit to the second central processing unit when the entire contents of the first memory unit are written to the second memory unit. And a means for outputting a permission signal for permission.

In addition to the above configuration, another CPU switching circuit according to the present invention supplies a read address to the first memory device and simultaneously writes the same address as the read address to the second memory device. It is provided with a means for supplying it as an address.

[0016]

When the CPU switching is instructed, the same address signal is output to the memory circuit used by the active system and the memory circuit used by the standby system to read information from the memory circuit used by the active system. The information is written into the memory circuit used by the standby system almost simultaneously with the read operation.

The above read operation and write operation are performed for the memory size of the memory circuit, and at the same time as reading the information read from the memory circuit used by the standby system at the same address as the memory circuit used by the active system. Write. When all the information in the memory circuit used by the active system is written in the memory circuit used by the standby system, the CPU
The switching permission signal for permitting the switching of is output.

As a result, the CPU of the standby system can be made to perform a process different from that of the CPU of the active system during the normal operation, and the inheritance process of the memory can be performed without the control of the CPU and the firmware.

[0019]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a memory circuit 1 (hereinafter referred to as an active memory circuit) used by an active CPU (not shown) has an address signal (AD
The D) 101, the write signal (WR) 103, and the read signal (RD) 104 are input, and the data signal (DATA) 102 is exchanged with the active CPU.

In the memory circuit 2 (hereinafter, referred to as a standby system memory circuit) used by the standby system CPU (not shown), the address signal (ADD) 111, the write signal (WR) 113, and the read signal are read from the standby system CPU. Signal (RD) 114 and a data signal (DAT) with the standby CPU.
A) 112 is given and received.

The active memory circuit 1 and the standby memory circuit 2 are dual port memories (DPM) which can be accessed bidirectionally.

The pulse generation circuit 3 includes an active memory circuit 1
Value (COUNT) 121 indicating the memory size of the
And a select signal (SEL) 122 and a clock signal (CL) for instructing switching between the active CPU and the standby CPU.
K) 123 is input and the address signal (ADD) 13
1 and a read (RD) / write (WR) signal 133 and a switching permission signal 134 are output.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

First, in the active memory circuit 1, the active memory C is used.
Since the address signal 101, the write signal 103, and the read signal 104 are input from the PU, the active memory circuit 1
The data signal 102 is exchanged between the active CPU and the active CPU.

Further, similarly to this, the standby system memory circuit 2
Since the address signal 111, the write signal 113, and the read signal 114 are input from the standby CPU, the data signal 112 is exchanged between the standby memory circuit 2 and the standby CPU.

As described above, the active CPU and the standby CPU perform their own processing operations by using the active memory circuit 1 and the standby memory circuit 2, respectively. When the CPU of the active system and the CPU of the standby system are operating, respectively, and when it becomes necessary to switch the CPU due to a failure or the like, the select signal 122 is output to the pulse generation circuit 3.

When the select signal 122 is input, the pulse generating circuit 3 outputs the same address signal 131 to the active memory circuit 1 and the standby memory circuit 2 and also outputs the read signal 133 to the active memory circuit 1. , And outputs a write signal 133 to the standby system memory circuit 2.

As a result, the information read from the active memory circuit 1 is written into the standby memory circuit 2 at the same address as the active memory circuit 1. Reading from the active memory circuit 1 and writing to the standby memory circuit 2 are simultaneously performed.

The pulse generating circuit 3 repeats the above operation for the number of times of the inputted counter value 121. That is, the pulse generation circuit 3 outputs the address signal 131, the read signal 133 to the active memory circuit 1 and the write signal 133 to the standby memory circuit 2 as many times as the input counter value 121.

Therefore, all the information in the active memory circuit 1 (information for the memory size) is read and written in the standby memory circuit 2, so that the contents of the active memory circuit 1 and the standby memory circuit 2 are read. Are the same.

Here, the information of the standby system memory circuit 2 disappears when the information of the active system memory circuit 1 is written, but the standby system memory circuit 2 stores the information which may disappear. I shall. Further, when writing information from the active memory circuit 1 to the standby memory circuit 2, the active CP
The U and the CPU of the standby system are in an operating state where the system does not stop.

When the information in the active memory circuit 1 is repeatedly written in the standby memory circuit 2 the number of times of the counter value 121, the pulse generating circuit 3 outputs a switching permission signal 134 to the standby CPU. Standby CPU is switching permission signal 1
In response to 34, the operation is started as the active system.

In this way, the CPU from the standby system to the active system
Under the control of the pulse generation circuit 3 in response to the select signal 122 for instructing switching of the active memory circuit 1, the information in the active memory circuit 1 is read and the information is written in the standby memory circuit 2 at the same time. When all the information in the memory is written in the standby memory circuit 2, the switching permission signal 1
By outputting 34, the CPU of the standby system can be made to perform a process different from that of the CPU of the active system during the normal operation, and the active memory circuit 1 to the standby memory circuit 2 can be operated without control of the CPU or firmware. Can be inherited. It should be noted that the above effect is more remarkable in a system in which a large amount of data needs to be held in the working memory.

[0035]

As described above, according to the present invention, the first memory uniquely used in the first central processing unit in response to the switching instruction signal instructing the switching from the standby system to the active system. The content of the device is read and the read content is second
Simultaneously write to a second memory device that is uniquely used in the central processing unit of the first memory device, and when the entire contents of the first memory device are written to the second memory device, By outputting a permission signal for permitting switching to the central processing unit 2 in the standby mode, the CPU of the standby system can perform a different process from the CPU of the active system during normal operation, and there is no control of the CPU or firmware. This has the effect of allowing the memory inheritance process to be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Working memory circuit 2 Standby memory circuit 3 Pulse generator circuit

Claims (3)

[Claims] 1. A CPU switching of an information processing system including first and second central processing units, wherein the second central processing unit is used as a standby system when the first central processing unit is used as an active system. A circuit for reading and reading the contents of a first memory device uniquely used by the first central processing unit in response to a switching instruction signal for instructing switching from the standby system to the active system. The contents of the second
Means for simultaneously writing to a second memory device that is uniquely used in the central processing unit of the first central processing unit, and the first central unit when all contents of the first memory device are written to the second memory device. And a means for outputting a permission signal for permitting switching from the processing unit to the second central processing unit. 2. A means for supplying a read address to the first memory device and at the same time supplying a same address as the read address to the second memory device as a write address. CPU described
Switching circuit. 3. The CPU switching circuit according to claim 1, wherein the first and second memory devices are bidirectionally accessible.