JPS62272333A - Tracer system - Google Patents

Abstract

PURPOSE:To effectively use a memory by storing a micro instruction address, the first data, the last data, and the number of times of continuity when the same micro instruction address continues. CONSTITUTION:A memory 1 has enough bit width to store the micro instruction address, by which a control storage where a microprogram is stored is accessed, and data consisting of plural bits indicating the state of an information processor incorporating this control storage, and the memory 1 has enough words to store data in the period from the occurrence to the detection of each of almost all troubles. If the same micro instruction address continues, this micro instruction address, the first data, the last data, and the number of times of continuity are stored in the memory 1. Thus, addresses and data in the period longer than that corresponding to the number of words of the memory 1 are stored and the memory 1 is effectively used without keeping back duplicate data.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Technical Field The present invention relates to a tracer method, and more particularly to a tracer method for storing the history of the internal state of an information processing device.

Circle B ■ Conventionally, in this type of tracer method, a tracer circuit composed of a memory, an address circuit, and a control circuit writes data indicating the internal state of an information processing device to the memory while changing the write address. I go all the time. When data is written to all words of this memory, the write address is returned to the initial address and the data is simply written to the word that was once written.

This operation continues until the information processing device detects a failure. When a fault is detected, the tracer circuit stops updating the write address and writing to the memory via the control circuit,
Data indicating the internal state of the information processing device is stored in the memory with the maximum number of words in the memory going back from the failure detection.

In such a conventional tracer method, data continues to be written to memory while updating the write address every clock until a failure is detected. However, during the operation of information processing equipment, certain signals within the equipment In order to hold the data until the occurrence, etc., the internal state of the device often remains constant for several clocks, and the same data is written to the memory for these several clocks each clock. The problem was that the same data remained for several words on the top, and the memory was not used effectively.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional methods as described above, and an object of the present invention is to provide a tracer method that can effectively use memory.

λ1 Tatedan1 The tracer method according to the present invention is a tracer method that stores data indicating the internal state of an information processing device, and is a tracer method that stores data indicating the internal state of an information processing device. I! When microinstruction addresses from the device are consecutive at the same address, the microinstruction address, the first data, the last data, and the number of consecutive times are stored.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the tracer circuit according to one embodiment of the present invention includes a memory 1, a data register 2, a comparison circuit 3, and a counting circuit 4.
, a data switching circuit 5 , a state holding circuit 6 , an address counter circuit 7 , an address switching circuit 8 , a timing circuit 9 , and a control circuit 10 .

FIG. 2 is a more detailed circuit diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. The configuration and operation of an embodiment of the present invention will be explained in detail using FIG. 1 and FIG. 2.

Memory 1 stores a microinstruction address for accessing a control memory (not shown) that stores a microprogram, and a multi-bit data indicating the status of an information processing device (not shown) containing this i-control memory. It has sufficient bit width to store data, and has a sufficient number of words to store data for the period from the occurrence of a fault to the detection of that fault for most faults. Write data is written into the memory 1 in the word specified by the address output from the address 1ro circuit 8 when the control circuit 10 instructs it with a write instruction signal, and when the control circuit 10 instructs it with a write instruction signal. If not, the contents of the word specified by the address output from address switching circuit 8 are read from memory 1.

The data register 2 inputs and holds the microinstruction address input to the memory 1.

The microinstruction address held in the data register 2 is sent to the comparison circuit 3.

The comparison circuit 3 is composed of a comparator 30 and an OR circuit 31. The microinstruction address input to the memory 1 and the microinstruction address held in the data register 2 are input to the comparator 30. The addresses are compared, and when these addresses do not match, a mismatch signal is output. That is, when the address inputted last time to the memory 1 and the address inputted this time do not match, a mismatch signal is output. The OR circuit 31 ORs this mismatch signal and the all 1 signal from the 51 number circuit 4, and sends the output signal to the counting circuit 4, data switching circuit 5, and timing circuit 9.

Counting circuit 4 consists of register 40, +17 dar 41, and all 1s.
It consists of a detection circuit 42, a register 40, and a register 40.
The adder 41 forms a counter. +17dar 4
1 inputs all bits of register 40 and adds +1 to its contents.
is added and returned to register 40. Register 40 is +17
The output of the register 41 is always set, and when the comparator circuit 3 detects an address mismatch, the contents of the register 40 are reset in priority to the setting of the output of the +17 register 41. Further, the register 40 has the same bit width as the microinstruction address.

The all 1 detection circuit 42 inputs the output of the register 40,
It detects that all bits of the register 4o are "1" and outputs an all-1 signal. This all-1 signal indicates that the counter formed by the register 40 and the +17 counter 41 cannot count any more. 1 to reset the count value. Therefore, this all-1 signal is used after being ORed with the mismatch signal in the OR circuit 31, and is used in the register 4.
Resetting to 0 is performed using this ORed signal.

The data switching circuit 5 is composed of a cutter 50 and switches between the microinstruction address and the count value of the counting circuit 4 and inputs the same into the memory 1. That is, when the microinstruction addresses inputted to the memory 1 are the same consecutive addresses, the data switching circuit 5 operates to select the microinstruction address first and then select the count value thereafter. The output of the OR circuit 31 is used as this selection signal, and when this selection signal is "1", a microinstruction address is selected.

The state holding circuit 6 includes a register 60 and three AND circuits 6.
1, register 62, OR circuit 63, and NOT circuit 6
4. The register 60 stores and holds mask data specifying valid conditions among the stop conditions. This mask data is given externally,
It is stored in the register 60 by a mask set signal from the outside.

The AND circuit 61 ANDs the 3-bit output of the register 60 and the stop condition designated by each pit and outputs a stop signal. For this stop condition, detection signals of various failures within the information processing device are used. The register 62 inputs the stop signal from the AND circuit 61, stores and holds this stop signal, and is reset and held by an operation start signal from the outside. Initialize the stop signal.

The OR circuit 63 receives the 3-bit stop signal of the register 62,
OR with the external forced stop signal.

Both of these signals indicate that writing of data to memory 1 is stopped. The NOT circuit 6.4 inverts the output from the OR circuit 63 and outputs a signal indicating that data writing to the memory 1 is active. This signal is used as a set signal to set a stop signal in register 62.

The address counter circuit 7 includes a register 70 and a +17 der 7.
1 and an adder 72.

The register 70 and the +17 register 71 form a counter for creating the write address of the memory 1. +17dar71
inputs all bits of register 7o, and adds + to this input content.
1 is added and returned to the register 70, and the register 70 sets the output from the +17 adder 71 using the signal from the control ill@8 as a set signal.Adder 72 sets the output from register 7
Input the write address of o and external subtraction data, subtract the subtraction data from this write address, output the subtraction result, and use it as a read address for memory 1.
Used to create a relative address from a fixed write address. The output of register 70 and +17 der 71
The output of the adder 72 and the output of the adder 72 are sent to the address switching circuit 8.

The address switching circuit 8 is composed of switching devices 80 and 81, and the switching device 80 controls the count value of the write address counter output from the register 70 and the next count value of the write address counter output from the +17 der 71. It is switched by a signal from the circuit 10. In addition, the switch 80 updates the contents of the register 70 and operates so that when microinstruction addresses are the same and consecutive, the switcher 80 outputs the address where the previous write at array was updated as the write address of the first microinstruction address. , as the write address of the second and subsequent microinstruction addresses, an address that is an updated write address of the first microinstruction address is output, and this address is repeatedly outputted until the microinstruction address changes. When the microinstruction address changes, an updated write address of the second and subsequent microinstruction addresses is output.

The switch 81 switches between the write address output from the switch 8o and the read address output from the adder 72 in response to a signal output from the state holding circuit 6 indicating that writing to the memory 1 is active. This signal is
1” selects the write address.

The timing circuit 9 is composed of a 1-bit register 90 and an OR circuit 91. 1 bit register 90
always sets a signal obtained by ORing the mismatch signal of the comparison circuit 3 and the all-1 signal of the counting circuit 4, and outputs a signal delayed by one clock from this signal. OR circuit 91 is register 9
A signal indicating when the output of the OR circuit 31 input to 0 and the output of the register 90 is detected, and when the comparator circuit 3 detects an address mismatch, and when the first address match following the address mismatch is detected. Output.

The control circuit 10 is constituted by an AND circuit 100, which ANDs a signal indicating that data writing to the memory 1 is in operation and the output of the OR circuit 91. This AND signal is sent to the address counter circuit 7 and is used as an update instruction for the write address counter. Furthermore, this AND signal is applied to the address switching circuit 8.
and is used as a selection signal for the switch 80 as a signal instructing the output of the next count value of the write address counter. Further, the control circuit 10 sends a signal indicating that writing to the memory 1 is active, which is output from the state holding circuit 6, to the memory 1 as it is as a write instruction signal to the memory 1.

In this way, when microinstruction addresses are consecutive at the same address, by storing this microinstruction address, the first data, the last data, and the number of consecutive times in memory 1, it is possible to store the microinstruction address for a period longer than the number of words that memory 1 has. Addresses and data can be stored in the memory 1, and the memory 1 can be used effectively without leaving duplicate data.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when microinstruction addresses are consecutive at the same address, the microinstruction address, the first data, the last data, and the number of consecutive times are stored in the memory. This has the effect of making it possible to use memory effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a more detailed circuit diagram showing one embodiment of the present invention. Explanation of symbols of main parts 2... Data register 3... Comparison circuit 4... Counting circuit 5... Data switching circuit 8... Address switching circuit 9... Timing circuit 1o... Control circuit

Claims (1)

[Claims] A tracer method that stores data indicating the internal state of an information processing device, and when microinstruction addresses from the information processing device are consecutive at the same address, the microinstruction address, the first data, the last data, and the number of consecutive times. A tracer method that is characterized by being able to memorize.