JPS62242333A - Structure of bonding pad of semiconductor device - Google Patents
Structure of bonding pad of semiconductor deviceInfo
- Publication number
- JPS62242333A JPS62242333A JP8489586A JP8489586A JPS62242333A JP S62242333 A JPS62242333 A JP S62242333A JP 8489586 A JP8489586 A JP 8489586A JP 8489586 A JP8489586 A JP 8489586A JP S62242333 A JPS62242333 A JP S62242333A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- semiconductor device
- insulating film
- bonding pad
- aluminium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、多層アルミニウム配
線工程をもつ半導体装置のポンディング・ぐノド部の構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a structure of a bonding groove portion of a semiconductor device having a multilayer aluminum wiring process.
従来、この種の多重アルミニウム配線工程を有する半導
体装置におけるボンディングパッド部は。Conventionally, a bonding pad portion in a semiconductor device that has this type of multiple aluminum wiring process.
最終工程のアルミニウムによる一層構造であり。It has a single-layer structure made of aluminum in the final process.
その厚さもその工程で作られる厚さで決定されていた。Its thickness was also determined by the thickness produced in that process.
上述した従来の半導体装置のポンディング／ｆ ノド部
の構造では、ウェハー状態で半導体装置をプローバー等
のビン（金属合金で作られたもの）で強制的にキズを作
シ接触面を確保させる場合には。In the conventional structure of the bonding/f throat part of the semiconductor device described above, when the semiconductor device is forcibly scratched with a bottle (made of metal alloy) such as a prober while it is in a wafer state, a contact surface is secured. for.
キズがアルミニウム下部まで到達してしまうことがあり
、この後１組立工程で封入した場合、耐湿性が劣化する
という欠点がある。Scratches may reach the lower part of the aluminum, and if it is subsequently sealed in one assembly process, there is a drawback that moisture resistance will deteriorate.
その故に１本発明の目的は、耐湿性劣化を減少させるこ
とができる半導体装置のがンディングパノド部の構造を
提供することにある。Therefore, one object of the present invention is to provide a structure for a mounting pane of a semiconductor device that can reduce moisture resistance deterioration.
本発明によれば、多層アルミニウム配線工程を有する半
導体装置のがンディングパノド部が、少なくとも２層以
上のアルミニウムを重ね合せてなることを特徴とする半
導体装置のボンディングパッド部の構造が得られる。According to the present invention, it is possible to obtain a structure of a bonding pad portion of a semiconductor device having a multilayer aluminum wiring process, in which the bonding pad portion of the semiconductor device is formed by overlapping at least two or more layers of aluminum.
（＊′Ｘ
このように、多層のアルミニウムを重ね合せることによ
り、その厚さが厚くなシ、プローバー等のビンをアルミ
ニウム下部まで到達しにくくすることができる。又、ア
ルミニウムの重ね合せは。(*'X) By stacking multiple layers of aluminum in this way, it is possible to make it difficult for thick bottles such as probers to reach the bottom of the aluminum.
マスクを一部変更するだけで容易に実現することができ
る。This can be easily achieved by only partially changing the mask.
以下１本発明の実施例について図面を参照して詳細に説
明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図は本発明による一実施例の構造を示した上面図、
第２図は第１図のＡ −Ａ’で切ったときの断面図であ
る。FIG. 1 is a top view showing the structure of an embodiment according to the present invention;
FIG. 2 is a sectional view taken along line A-A' in FIG.
これら図において、１は一部アルミニウムを示し、その
外周縁が第１絶縁膜５で覆われている。In these figures, 1 partially represents aluminum, the outer periphery of which is covered with a first insulating film 5.
２は二層アルミニウムで一層アルミニウムｌに重ね合わ
されており、その外周部は第１絶縁膜５の内周部を覆っ
ている。又、二層アルミニウム３の外周縁は第２絶縁膜
６で覆われている。又、４は第１絶縁膜５と一部アルミ
ニウム１の境界を示し。Reference numeral 2 is a double layer of aluminum, which is superimposed on a single layer of aluminum 1, and its outer periphery covers the inner periphery of the first insulating film 5. Further, the outer peripheral edge of the double-layer aluminum 3 is covered with a second insulating film 6. Further, 4 indicates the boundary between the first insulating film 5 and a portion of the aluminum 1.
２は第２絶縁膜６と二層アルミニウム３の境界を示して
いる。2 indicates the boundary between the second insulating film 6 and the double layer aluminum 3.
このようにして、ボンディング・ぐラド部の厚さを厚く
することによシ、プローバー等のキズ及び水分等の浸入
を防ぐことができる。In this way, by increasing the thickness of the bonding/grading portion, it is possible to prevent scratches from probers, etc., and infiltration of moisture.
なお、上記実施例では、二層アルミニウム工程までを有
するものを図示しているが、三層及び多層アルミニウム
工程までを有する場合には、さらに重ねてアルミニウム
の厚さを厚くすることもできる。In addition, although the above-mentioned example shows an example having up to a two-layer aluminum process, in the case of having up to a three-layer and multi-layer aluminum process, the thickness of the aluminum can be increased by further stacking.
以上説明したように０本発明は、多層アルミ配線工程を
有する半導体装置において、各層アルミを重ねることに
よシ、カンディング・ぐラド部の厚さを厚くすることが
でき、そのだめに、ゾロ−パー等のキズ（接触によって
できるもの）及び水分等の浸入を防ぐことができ、耐湿
性の向上に効果がある。As explained above, in a semiconductor device having a multilayer aluminum wiring process, the thickness of the canding/gradient portion can be increased by overlapping each layer of aluminum, and as a result, - It is possible to prevent scratches such as those caused by contact with the material and infiltration of moisture, etc., and is effective in improving moisture resistance.
第１図は本発明によるボンディング・やラド部の構造の
一実施例を示した上面図、第２図は第１図のＡ −Ａ’
で切ったときの断面図である。
１・・・一層アルミニウム、２・・・第２絶縁膜と二層
アルミニウムとの境界、３・・・二層アルミニウム。
４・・・第１絶縁膜と一部アルミニウムとの境界、５・
・・第１絶縁膜、６・・・第２絶縁膜。FIG. 1 is a top view showing an embodiment of the structure of the bonding/rad portion according to the present invention, and FIG.
FIG. 1... Single layer aluminum, 2... Boundary between the second insulating film and double layer aluminum, 3... Double layer aluminum. 4. Boundary between first insulating film and part of aluminum, 5.
...first insulating film, 6... second insulating film.
Claims (1)
ンディングパッド部が、少なくとも２層以上のアルミニ
ウムを重ね合せてなることを特徴とする半導体装置のボ
ンディングパッド部の構造。1. A structure of a bonding pad portion of a semiconductor device having a multilayer aluminum wiring process, characterized in that the bonding pad portion of the semiconductor device is formed by stacking at least two or more layers of aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8489586A JPS62242333A (en) | 1986-04-15 | 1986-04-15 | Structure of bonding pad of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8489586A JPS62242333A (en) | 1986-04-15 | 1986-04-15 | Structure of bonding pad of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242333A true JPS62242333A (en) | 1987-10-22 |
Family
ID=13843475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8489586A Pending JPS62242333A (en) | 1986-04-15 | 1986-04-15 | Structure of bonding pad of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242333A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5136364A (en) * | 1991-06-12 | 1992-08-04 | National Semiconductor Corporation | Semiconductor die sealing |
| US5394013A (en) * | 1990-11-28 | 1995-02-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with an elevated bonding pad |
| KR100284860B1 (en) * | 1992-08-31 | 2001-06-01 | 맥켈러 로버트 루이스 | How to protect the confidentiality of integrated circuit |
-
1986
- 1986-04-15 JP JP8489586A patent/JPS62242333A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5394013A (en) * | 1990-11-28 | 1995-02-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with an elevated bonding pad |
| US5136364A (en) * | 1991-06-12 | 1992-08-04 | National Semiconductor Corporation | Semiconductor die sealing |
| KR100284860B1 (en) * | 1992-08-31 | 2001-06-01 | 맥켈러 로버트 루이스 | How to protect the confidentiality of integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62242333A (en) | Structure of bonding pad of semiconductor device | |
| JPH06326150A (en) | Pad structure | |
| JPH08180324A (en) | Thin-film magnetic head | |
| JPH05267460A (en) | Method of generating flattened pattern to wiring layer | |
| JP3645450B2 (en) | Semiconductor device | |
| JPH0621061A (en) | Semiconductor device | |
| JPS6325951A (en) | Semiconductor device | |
| JP2867488B2 (en) | Semiconductor device | |
| KR960035780A (en) | Method for manufacturing semiconductor device | |
| JPS5852854A (en) | Semiconductor device | |
| JPH0433356A (en) | Manufacture of semiconductor device | |
| JPH0546987B2 (en) | ||
| JPS63308924A (en) | Semiconductor device | |
| JPH02161755A (en) | Semiconductor device | |
| JPS62291145A (en) | Semiconductor device | |
| JPH02297953A (en) | Semiconductor device | |
| JPS61224438A (en) | Wiring pattern shape of semiconductor device | |
| JPS61188946A (en) | Multilayer interconnection semiconductor integrated circuit | |
| JPS6310542A (en) | Semiconductor device | |
| JPS60102781A (en) | magnetoresistive element | |
| JPH0499362A (en) | semiconductor equipment | |
| JPH05152447A (en) | Semiconductor integrated circuit device | |
| JPH02231735A (en) | Semiconductor device | |
| JPH05291259A (en) | Semiconductor device | |
| JPS63283042A (en) | Semiconductor element |