JPS6310542A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a manufacturing yield of a semiconductor device as well as reliability on them, thereby decreasing a hillock growth that is liable to arise easily when an insulating film is formed on an interconnection layer by forming an interconnection having a large capacity that is likely to require a line width of more than 10mum among film interconnections in accordance with a parallel arrangement or lattice-type arrangement of film interconnections consisting of a plurality of lines having the line width of less than 10mum. CONSTITUTION:Even though the line width of film interconnections comprising metallic films requires more than 10mum, the film interconnections having the line width of less than 10mum are arranged in parallel or in the form of lattice and the maximum sizes of interconnections do not exceed 10mum. For instance, while the film interconnections comprising a single line require their line width more than 24mum, the film interconnections comprising three lines 1a, 1b, and 1c having the line width W ranging 8-10mum are arranged in parallel and contact diffused layers 2 at 3a, 3b, and 3c respectively. On the other hand, while it is necessary for bonding pads 4 to have a broad area, the film interconnections 4a having the line width W ranging 8-10mum are arranged in the form of lattice and cover a broad bonding pad area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming a wiring layer of a semiconductor device using a metal film as an electrode wiring layer.

[Conventional technology]

2. Description of the Related Art Conventionally, metals (mainly i) have been used for electrode wiring layers of semiconductor devices. FIG. 3 is a cross-sectional view of an element showing a wiring structure using Al wiring.

In FIG. 3, after an insulating film 7 is formed on a silicon substrate 6, an Al wiring layer 9 is formed. On top of this, an insulating film 8 is formed which becomes a second insulating film in the case of a pudge page or two-layer wiring structure. In order to obtain such a structure, the insulating film 8 is usually formed at about 400° C. by the CVD method.

[Problem that the invention seeks to solve]

During the conventional insulating film formation described above, hillocks 10 are likely to occur on the Al wiring layer. This hillock 1O causes abnormal growth of the insulating film on the A/wiring, which weakens the mechanical strength of the insulating film and causes cracks 11. Kura, Ri 11 is A
(l) This causes a short circuit between the second aluminum wiring and the first aluminum wiring layer on the insulating film on the wiring, and corrosion of the Al wiring due to penetration of chemicals through cracks, etc. Yield or reliability was significantly reduced.

[Means for solving problems]

The wiring layer contains stress generated at the time of film formation, and this stress appears as cracks and cracks due to heat treatment and the like when forming an insulating film on the wiring layer. It is known that hillocks occur more frequently as the line width of the wiring layer increases, and decrease as the line width becomes smaller. This is because the amount of residual internal stress increases depending on the line width. 3, meaning different things;
Therefore, in the present invention, the wiring layer is designed so that the maximum dimension of the wiring layer is within 10 μm in order to eliminate the remaining internal stress and reduce the growth of hillocks.

〔Example〕

Next, the present invention will be explained by examples.

FIG. 1 is a partial plan view of a wiring layer according to an embodiment of the present invention. In FIG. 1, three film wirings 1a each have a line width W of 8 μm, which does not exceed 10 μm, whereas a single line requires a line width of 24 μm or more.

lb, IC are arranged in parallel, and the diffusion layer 2 and each 3a
, 3b and 3c.

In FIG. 2, the bonding pad 4, which requires a large area, covers a 3 m pad with a line width W of 8 μm which does not exceed 10 μm.

Note that although the above description has been made of a single-layer AlQ wiring material, the present invention is also applicable to several types of multi-layered metal films or alloy layers.

〔Effect of the invention〕

As explained above, the present invention enables film wiring made of a metal film in a semiconductor device to have a line width of 10 μm or more, by arranging film wiring of l Q am or less in parallel or in a lattice pattern. By reducing the maximum dimension of 10 μm or less to eliminate the remaining internal stress, the growth of hillocks that are likely to occur when forming an isolation film on the wiring layer is reduced, and the manufacturing yield and reliability of semiconductor devices are improved. It is possible to improve your sexuality.

[Brief explanation of drawings]

FIG. 1 is a partial plan view of a wiring layer according to an embodiment of the present invention;
FIG. 2 is a plan view of an example of an electrode pad according to the present invention, and FIG. 3 is a cross-sectional view of a semiconductor element for explaining hillock failure in film wiring. Ia, 1b, 1c・-=film wiring of 10 μm or less, 2...
...Diffusion layer, 3a, 3b, 3c...Contact, 4-----9-iy di, G pad, 4a...
・・・Current line, 6...Silicon substrate, 7...
...First insulating film, 8... Second insulating film, 9-
゛-Wiring layer, 10°゛...Hillock, 11...
·crack. Koma 2 times 3 fields

Claims (1)

[Claims] In a semiconductor device having a film wiring made of a metal film formed on a semiconductor substrate via an insulating film, among the film wirings, a large-capacity wiring that requires a line width of 10 μm or more has a line width of 10 μm or more. A semiconductor device characterized in that it is formed by a parallel arrangement or a lattice arrangement of a plurality of film wirings of 10 μm or less.