JP2867488B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2867488B2 JP2867488B2 JP1289468A JP28946889A JP2867488B2 JP 2867488 B2 JP2867488 B2 JP 2867488B2 JP 1289468 A JP1289468 A JP 1289468A JP 28946889 A JP28946889 A JP 28946889A JP 2867488 B2 JP2867488 B2 JP 2867488B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- stress
- bonding pad
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 15
- 230000005012 migration Effects 0.000 description 7
- 238000013508 migration Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 102100027340 Slit homolog 2 protein Human genes 0.000 description 1
- 101710133576 Slit homolog 2 protein Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、AL多層配線構造の半導体装置におけるスト
レスマイグレーションに対して強靭な構造を有する構造
を提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a structure having a structure resistant to stress migration in a semiconductor device having an AL multilayer wiring structure.
［従来の技術］ 半導体装置の高密度集積化にともないAL配線層の多層
化が標準的に行なわれるようになってきた。ところが、
配線の多層化によりストレスマイグレーションという新
しい問題が発生してきた。[Prior Art] With the high-density integration of semiconductor devices, multi-layered AL wiring layers have been standardized. However,
A new problem called stress migration has arisen due to the multi-layered wiring.
ストレスマイグレーションは、主にモールドパッケー
ジを行なう製品に顕著にみられるが、実際には製造の過
程で起きている。第２図にAL2層配線を例に説明する。
下層AL配線層21上に、層間絶縁膜22が形成されVIAホー
ルを介して下層AL配線層21と接続された上層AL配線層23
があり、保護膜としてパシベーション膜24で覆われた構
造の半導体装置では、これらの製造工程特に上層AL配線
層の形成以降の工程に於ける熱処理で、第２図の矢印で
示したような圧縮応力や引っ張り応力などによるストレ
スが上層AL配線23,下層AL配線21に加わる。この場合特
に下層配線23には大きなストレスが加わるため通常スト
レスマイグレーションは、この下層配線21に生じること
が多い。第３図にその例を示す。下層配線層21の進行方
向に垂直に発生しているノッチ25が、ストレスマイグレ
ーションが起きているところである。また半導体装置の
４隅の部分は特にモールドパッケージ実装時に集中的な
応力をうけるためAL配線で形成されているボンディング
パッドの変形、ボンディングパッドへ結線されるAL配線
の断線、さらにこれらのパターンの歪によるパシベーシ
ョン膜のクラックなどが発生している。The stress migration is remarkably observed mainly in a product which performs a mold package, but actually occurs during a manufacturing process. FIG. 2 illustrates an AL2 layer wiring as an example.
On the lower AL wiring layer 21, an interlayer insulating film 22 is formed, and the upper AL wiring layer 23 connected to the lower AL wiring layer 21 via a VIA hole.
In a semiconductor device having a structure covered with a passivation film 24 as a protective film, a heat treatment in these manufacturing processes, particularly in a process after the formation of the upper AL wiring layer, causes a compression as shown by an arrow in FIG. A stress such as a stress or a tensile stress is applied to the upper AL wiring 23 and the lower AL wiring 21. In this case, since a large stress is applied particularly to the lower wiring 23, normal stress migration often occurs in the lower wiring 21 in many cases. FIG. 3 shows an example. The notch 25 generated perpendicular to the traveling direction of the lower wiring layer 21 is where stress migration occurs. In addition, the four corners of the semiconductor device are subjected to intensive stress particularly during the mounting of the mold package, so that the bonding pad formed by the AL wiring is deformed, the AL wiring connected to the bonding pad is disconnected, and the distortion of these patterns is caused. Cracks and the like in the passivation film have occurred.
［発明が解決しようとする課題］ そこで本発明では第３図の様なストレスにより起きる
ストレスマイグレーションを緩和する配線構造を提供す
るものであり、特に半導体装置の４隅で発生し易いボン
ディングパッドの変形を防ぐものである。[Problems to be Solved by the Invention] Accordingly, the present invention provides a wiring structure for alleviating stress migration caused by stress as shown in FIG. It is to prevent.
［課題を解決するための手段］ 本発明の半導体装置は、スリットが設けられた１層目
のアルミニウム配線層と、前記１層目のアルミニウム配
線層の上層に設置された２層目のアルミニウム配線層
と、から構成されるボンディング用パッドを有する半導
体装置において、 前記１層目のアルミニウム配線層に設けられたスリッ
トは前記半導体装置の中心に向かう方向に沿って形成さ
れていることを特徴とする。[Means for Solving the Problems] A semiconductor device according to the present invention includes a first aluminum wiring layer provided with a slit, and a second aluminum wiring provided above the first aluminum wiring layer. And a slit provided in the first aluminum wiring layer is formed along a direction toward the center of the semiconductor device. .
また、前記ボンディング用パッドは前記半導体装置の
コーナー部に設置されていることを特徴とする。Further, the bonding pad is provided at a corner of the semiconductor device.
［実施例］ 第１図に本発明を示す。この図は半導体装置の４隅の
部分を示しており、１はALでできたボンディングパッド
であり、通常２層AL配線構造である上下の２層AL配線に
より形成される。尚、ここでは説明が分かりやすくする
ため下層AL配線３が形成された状態を現わしている。２
は下層AL配線で形成されたボンディングパッド上に形成
されたスリットである。本実施例ではスリット幅として
１〜３ミクロンのスリット２をこの半導体装置の中心方
向に向かって５〜60ミクロンの長さで形成した。FIG. 1 shows the present invention. This figure shows the four corners of the semiconductor device. Reference numeral 1 denotes a bonding pad made of AL, which is usually formed by upper and lower two-layer AL wirings having a two-layer AL wiring structure. Here, for the sake of simplicity of description, a state in which the lower AL wiring 3 is formed is shown. 2
Is a slit formed on the bonding pad formed by the lower AL wiring. In this embodiment, the slit 2 having a slit width of 1 to 3 microns is formed with a length of 5 to 60 microns toward the center of the semiconductor device.
［発明の効果］ 従来モールドパッケージ実装時に、半導体装置にかか
る応力は、特にその半導体装置の４隅４にエネルギーが
集中し易かった。そのためALでできているボンディング
パッドはALが柔らかい材料であるため塑性変形すること
があった。ところが本発明のようにボンディングパッド
にスリットパターンを設けることにより上から加わった
ストレスエネルギーをこのスリットで発散させるため、
ボンディングパッドの変形を完全に防ぐことができた。
また同時にこのAL配線層より上の層の材料に対してもス
トレスを緩和する効果が有るため層間絶縁膜、パシベー
ション膜のクラックに対しても抑制することができた。[Effects of the Invention] Conventionally, stress applied to a semiconductor device at the time of mounting a mold package tends to concentrate energy particularly at the four corners 4 of the semiconductor device. Therefore, the bonding pad made of AL may be plastically deformed because AL is a soft material. However, in order to disperse the stress energy applied from above by providing a slit pattern on the bonding pad as in the present invention, the slit is used,
The deformation of the bonding pad was completely prevented.
At the same time, cracks in the interlayer insulating film and the passivation film can be suppressed because the material of the layer above the AL wiring layer has the effect of reducing stress.
第１図が本発明の実施例を示す図である。１がボンディ
ングパッド、２がボンディングパッド上に設けたスリッ
トである。第２図が２層AL配線構造の断面構造図。第３
図がストレスマイグレーションの発生例を示す図であ
る。FIG. 1 is a diagram showing an embodiment of the present invention. 1 is a bonding pad and 2 is a slit provided on the bonding pad. FIG. 2 is a sectional structural view of a two-layer AL wiring structure. Third
The figure shows an example of the occurrence of stress migration.
Claims (2)
ム配線層と、前記１層目のアルミニウム配線層の上層に
設置された２層目のアルミニウム配線層と、から構成さ
れるボンディング用パッドを有する半導体装置におい
て、 前記１層目のアルミニウム配線層に設けられたスリット
は前記半導体装置の中心に向かう方向に沿って形成され
ていることを特徴とする半導体装置。1. A bonding pad comprising: a first aluminum wiring layer provided with a slit; and a second aluminum wiring layer provided above the first aluminum wiring layer. The semiconductor device according to claim 1, wherein the slit provided in the first aluminum wiring layer is formed along a direction toward a center of the semiconductor device.
置のコーナー部に設置されていることを特徴とする請求
項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said bonding pad is provided at a corner of said semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1289468A JP2867488B2 (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1289468A JP2867488B2 (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03149831A JPH03149831A (en) | 1991-06-26 |
| JP2867488B2 true JP2867488B2 (en) | 1999-03-08 |
Family
ID=17743668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1289468A Expired - Lifetime JP2867488B2 (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2867488B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0170316B1 (en) * | 1995-07-13 | 1999-02-01 | 김광호 | Pad design method of semiconductor device |
| JP4814770B2 (en) * | 2006-12-01 | 2011-11-16 | パナソニック株式会社 | Semiconductor integrated circuit |
| JP2008218442A (en) * | 2007-02-28 | 2008-09-18 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device and manufacturing method thereof |
-
1989
- 1989-11-07 JP JP1289468A patent/JP2867488B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03149831A (en) | 1991-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2867488B2 (en) | Semiconductor device | |
| US7847403B2 (en) | Semiconductor device having no cracks in one or more layers underlying a metal line layer | |
| JP3206243B2 (en) | Bonding pad and method of forming the same | |
| JP2697592B2 (en) | Pad structure of semiconductor device | |
| JPH061795B2 (en) | Multilayer wiring structure | |
| JPS5833705B2 (en) | Hands-on-hand training | |
| JP3645450B2 (en) | Semiconductor device | |
| JPS6325951A (en) | Semiconductor device | |
| US5179435A (en) | Resin sealed semiconductor integrated circuit device | |
| JPH05267460A (en) | Method of generating flattened pattern to wiring layer | |
| JPH06196478A (en) | Semiconductor device | |
| JPS605542A (en) | semiconductor equipment | |
| JPS63283042A (en) | Semiconductor element | |
| JPS6310542A (en) | Semiconductor device | |
| JP2770390B2 (en) | Semiconductor device | |
| JPH0462176B2 (en) | ||
| JPH03149829A (en) | Semiconductor device | |
| JPH04261023A (en) | Semiconductor device | |
| JP2990322B2 (en) | Semiconductor device | |
| JPH0289321A (en) | Semiconductor device | |
| JPH0661288A (en) | Wiring method for semiconductor integrated circuit | |
| JPS6153745A (en) | Aluminum multilayer interconnection | |
| JPS63143826A (en) | Semiconductor device | |
| JPH04211149A (en) | Resin sealed semiconductor integrated circuit device | |
| JPH03165037A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081225 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081225 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091225 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term |