JPS62236199A - Electrical erasure-type semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To set an optimum write/erase time to the write/erase characteristic of a memory cell transistor by providing a dummy memory cell transistor, a circuit writing and erasing information in said transistor and a read circuit. CONSTITUTION:The titled memory has a semiconductor nonvolatile memory 26 employing an electrically erasable memory cell transistor to store informa tion, bias circuits 12 and 13 to read, erase and write information in the dummy memory cell transistor 11 equivalent to a memory cell transistor to store infor mation, and the read circuit 14. As a result information in the dummy cell 11 is written, erased and read, whereby the characteristic of the memory cell transistor to store information can offer an optimum write/erase time. Informa tion can be detected through a sense amplifier and an I/O buffer 25.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an electrically erasable semiconductor nonvolatile memory (hereinafter referred to as E).
(abbreviated as FROM).

2. Description of the Related Art In a conventional EFROM, the write/erase time is uniquely determined by an internal timing circuit and cannot be changed. On the other hand, the write/erase time of a memory cell/transistor varies depending on the value of so-called process parameters such as the thickness of its oxide film, so the write/erase time set by the timing circuit may be affected by variations in process parameters, etc. The reality is that it cannot be said that it is optimal after considering the following.

In addition, in E FROM, after many write/erase cycles, the write/erase characteristics deteriorate due to the influence of electrons trapped in the oxide film of the memory cell transistor. The writing/erasing time set in 2 will not result in sufficient writing/erasing.

Problems to be Solved by the Invention As described above, in the conventional E FROM, the write/erase time is uniquely determined by the timing circuit, and the write/erase characteristics of the memory cell/transistor are not optimized. No □.

The present invention has been made in view of the above points, and an object of the present invention is to provide an adjustment means capable of setting a write/erase time optimal for the write/erase characteristics of a memory cell/transistor with a simple configuration. There is.

Means for Solving the Problems In order to solve the above problems, the present invention provides an E2FROM for storing information, as well as a dummy memory cell transistor equivalent to the memory cell transistor in the E2FROM. A circuit for writing/erasing and a circuit for reading data are provided.

Function The present invention uses the above-described configuration to perform writing/erasing on the dummy memory cell/transistor, and determines the writing/erasing time by reading the data. Write/erase time can be obtained.

Example The figure shows a configuration diagram of an E FROM according to an embodiment of the present invention.

In FIG. 1, 2 is an information storage section of an E FROM including a control system, 1 is a circuit block including dummy memory cell transistors, and 61.11 is a dummy memory cell transistor. It has exactly the same structure and characteristics as the memory cell transistors in the memory cell transistor array 26 that stores information. 12 and 13 are bias circuits for writing/erasing and reading the dummy memory cell transistor 11, and 1'4 is a read circuit thereof.

When writing/erasing of the E2FROM is executed, the dummy memory cell transistor 1 is simultaneously inserted into the memory cell transistor selected by the decoder 23 and 24 in the memory cell transistor array 26 for storing information.
1 is also written/erased through the booster circuit 27.

After writing/erasing for a certain period of time, the dummy memory
Cell transistor 11 moves to the read state. At this time, the selected cell in the memory cell transistor array 26 that stores information continues in its write/erase state. Dummy memory cell transistor 11
As a result of reading, the writing/
When erasing is performed, the writing/erasing of the selected memory φ cell transistor in the memory cell transistor array 26 that stores information is completed by the output signal 16. On the other hand, if it is determined that the dummy memory cell transistor 11 has not yet been written/erased to a predetermined level, the selected cell in the memory cell transistor array 26 that stores information remains unchanged. Writing/erasing continues, and the dummy cell 11 also shifts to the writing/erasing state again. Thereafter, the above operation is repeated, and the selected cell in the memory cell transistor array 26 continues to be programmed/erased until the dummy cell 11 is programmed/erased to a predetermined level.

The dummy cell 11 and the transistors in the memory cell array 26 for storing information have exactly the same structure.

By performing writing/erasing and reading of the dummy cell 11 based on the characteristics, the writing/erasing that is most suitable for the characteristics of the memory cell transistor for storing information is performed.
Erasing time can be obtained and information can be detected through the sense amplifier and human output buffer 25. In addition, by making the output signal 15 obtained from the dummy cell 11 readable by an external device (such as a CPU),
It is also possible to know the time when writing/erasing of E FROM is completed.

Effects of the Invention As described above, according to the present invention, it is possible to obtain write/erase times that are optimal for the characteristics of memory cells and transistors with an extremely simple circuit configuration, which is extremely useful in practice. .

BRIEF DESCRIPTION OF THE DRAWINGS The figure is a block diagram showing a schematic diagram of an embodiment of the present invention. 1...Circuit group including dummy memory cell transistor, 11...Dummy memory cell transistor
Transistor, 12.13...Bias circuit for writing/erasing and reading dummy memory cell transistor, 14...Reading circuit,
2...Block diagram of E2FROM including control system, 21...Control circuit, 22...Timing circuit, 23...X decoder, write/erase circuit , 24... Y decoder, write/erase circuit, 25... sense amplifier, input/output buffer circuit, 26... E2PROM memory cell.
Transistor array, 27...boost circuit.

Claims (1)

[Claims] In addition to semiconductor non-volatile memory using electrically erasable memory cell transistors that store information, dummy memory cell transistors equivalent to the memory cell transistors that store said information are used for writing/erasing and An electrically erasable semiconductor nonvolatile memory characterized by having a bias circuit for reading and a readout circuit.