JPS62234374A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve yield by a method where in a plurality of floating gate electrodes are provided above a drain region so as to partially overlap each other and a gate electrode which has capacitive couplings with a plurality of the floating gate electrodes is provided. CONSTITUTION:A plurality of conductive layers 6 and 6' which are to be floating gates are provided corresponding to a source region 2 and a drain region 3. The conductive regions 6 and 6' have thin insulating film regions 5 and 5' which have high capacitive couplings with the drain region 3 and a control gate 8 which have capacitive couplings with the floating gate electrodes is provided above the floating gates. Writing and erasing operation can be performed by the exchange of electrons with the floating gates 6 and 6' through the thin insulating film regions 5 and 5' and accumulated electrons carry their holding characteristics independently in accordance with the properties of the insulating films surrounding the floating gates 6 and 6'. With this constitution, as all of a plurality of the floating gates are hardly defective, the yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a nonvolatile semiconductor memory device in which information can be changed electrically.

2. Description of the Related Art A conventional electrically erasable nonvolatile semiconductor memory device, as shown in the cross-sectional view of FIG. A memory function is provided by storing electrons in the electrically insulated gate electrode 6, and the electrons are supplied from the drain region 3 through the thin gate insulating film 5. Furthermore, the charges accumulated in the insulated gate electrode 6 are surrounded by the insulating films 4 and 6 as well as the upper insulating film 7 formed to cover the insulated gate electrode 6, and are transmitted from the outside through the control gate electrode 8. It is stored semi-permanently unless it is released by a strong electric field.

Problems to be Solved by the Invention However, even with such conventional techniques, the insulating film 4,
Due to some defect in 5.7, poor charge conservation appears.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a structure in which a plurality of insulated gates, so-called floating gate electrodes, for accumulating charges are arranged in a distributed manner.

Function According to the present invention, since the insulated gate electrodes for charge storage are distributed, the locations of the stored charges are different.
Even if insulating film defects exist in a dispersed manner, there is a much higher possibility that at least one insulated gate electrode will operate normally, and therefore the probability that it can be used as a normal memory device, that is, the yield, increases. It turns out. Note that this does not adversely affect normal operations such as writing and erasing.

Embodiment FIG. 1 is a sectional view showing an embodiment of a memory device of the present invention.
FIG. 2 is a plan view thereof. A plurality of conductive regions 6 and 6' serving as floating gates are provided for a source region 2 and a drain region 3 formed on a semiconductor substrate 1. These conductive regions 6, 6' each have a thin insulating film region 6 and a bridge which are strongly capacitively coupled to the drain region 3. 8 is a so-called control gate which is capacitively coupled onto the floating gate.

In the write/erase operation, electrons are exchanged with the floating gate 6.degree. 6' through the thin insulating film regions 6 and 6', as in the prior art. The accumulated electrons have independent retention characteristics depending on the properties of the insulating film surrounding the floating gates 6 and 6'. and each floating gate 6. θ' affects the channel portion through the underlying gate films 4 and 4'. Also, these floating gates6. Since the source region 2 and the drain region 3 are arranged in series, the retention characteristics of the memory cell are determined by whichever of the floating gates and 6' has better retention characteristics. ,
Its characteristics will be significantly improved.

Moreover, this makes it rare for all of the plurality of floating gates to become defective, and product yield is also improved.

Effects of the Invention As described above, according to the present invention, the reliability is significantly increased with an extremely simple structure without changing the conventional manufacturing method, and it is extremely useful in practice.

[Brief explanation of drawings]

1 and 2 are a sectional view and a plan view showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. Source region, 3. Drain region, 4, 4'... Gate insulating film, 6, 61... Thin gate insulating film, 6
, 6'...Floating gate, 8...
...Control Kate. Name of agent Patent attorney Toshio Nakao and one other person 1985 Patent application No. 7J3570-2 Name of invention Semiconductor storage device 3 Person making amendments Relationship to the case Patent application
Appointment Address: 1006 Kadoma, Kadoma City, Osaka Prefecture
Name (584) Matsushita Electric Industrial Co., Ltd. Representative: Mr. Fujimoto 4 Agent Address: 571 Address: 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Date of 5 Amendment Order: June 24, 1988 7, Amended ``Figure 2'' on page 4, line 1e of the statement of contents of ``Figure 3''
I will correct it.

Claims (1)

[Claims] a source region and a drain region formed on a semiconductor substrate;
A semiconductor memory device comprising a plurality of floating gate electrodes formed on the drain region so that portions of the floating gate electrodes overlap, and a gate electrode capacitively coupled to the plurality of floating gate electrodes.