JPH0582748B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an electrically rewritable semiconductor nonvolatile memory device and a writing method therefor. [Prior Art] An electrically rewritable semiconductor non-volatile memory device (hereinafter referred to as EEPROM) having an insulated gate field effect transistor structure uses naturally occurring capture centers at the interface of different types of insulating films to capture carriers. ing. MNOS and MAOS type EEPROMs and floating type EEPROMs that use artificial potential well formation are generally known. [Problems to be Solved by the Invention] The EEPROM described above performs carrier injection using direct tunneling or Fauler-Nordheim tunneling current through an insulating film formed on a silicon substrate. Therefore, in consideration of capture efficiency, a high voltage of 20 V or more is applied during writing. Therefore, in a memory array in which the memory transistors constituting the EEPROM mentioned above are arranged in a matrix, the address
A cell structure in which the MOS transistor is provided separately from the memory transistor is required. The area of this memory cell becomes large, and it is difficult to reduce the area of this memory cell. This conventional memory cell is shown in FIG. As shown in FIG. 2, the memory cell is composed of two transistors, an address transistor a and a memory transistor b. An impurity layer 3 is provided between an impurity layer 1 serving as a source and a drain, and an impurity layer 2. Therefore, the memory cell area is determined by the need for an impurity layer 3 in the semiconductor region between address transistor a and memory transistor b, and by taking into account the overlay accuracy when manufacturing a semiconductor nonvolatile memory device. Since it requires minutes,
Miniaturization is difficult. Furthermore, since the gate insulating film of memory transistor b is composed of an ultra-thin insulating film, when a high voltage during writing is applied to the impurity layer 2, which is the drain region, the gate insulating film near the drain region is damaged. However, there are disadvantages in that the number of times of writing is limited and insulation film breakdown occurs. In recent years, with the development of VLSI, there has been a demand for larger capacity storage elements, forcing the miniaturization of memory cells. Therefore, there is an increasing demand for low voltage drive of EEPROM. However, in general, low-voltage driving is achieved by thinning the gate insulating film of the transistor, so the electric field during EEPROM writing or erasing can damage the gate insulating film or cause drain breakdown, causing This is a major problem as it causes instability in physical characteristics and deterioration due to changes over time. Therefore, as seen in Japanese Patent Application Publication No. 58-500683, for example, in semiconductor non-volatile memory, the insulating film under the gate electrode has a three-layer structure (SONOS structure) of silicon oxide, silicon nitride, and silicon oxide, and the gate voltage Some attempt to achieve stable operation at all times by increasing the withstand voltage. In addition, as seen in the above publication and Japanese Patent Publication No. 57-502024, three gate electrodes are provided on a semiconductor substrate, each insulated by an insulating layer,
One memory transistor and a pair of access transistors are formed on both sides of the memory transistor, and the memory transistor is an MNOS type in which the insulating film under the gate electrode has a two-layer structure of silicon dioxide and silicon nitride, and an impurity layer that becomes the source and drain. There are also products that do not require an impurity layer between them. However, with such semiconductor nonvolatile memory (EEPROM), information is written and erased using physical phenomena unique to the material, such as tunneling, as described above, so it is difficult to use circuit storage means. In comparison, the writing speed is significantly slower. Therefore, the problem that the range of use is limited remains unsolved. Furthermore, in the latter case, when erasing, writing, and reading information, it is necessary to individually control each gate electrode of the three transistors that make up each memory cell, so the control circuit and The wiring becomes complicated, which is inconvenient when a large number of memory cells are arranged in an integrated manner to increase the capacity. The present invention has been made in view of the current situation, and it is possible to miniaturize the area of memory cells, improve the withstand voltage with respect to gate voltage, and realize high-speed writing, as well as erase, write, and read information. The purpose of the present invention is to provide a semiconductor non-volatile memory device and a method for writing information thereto in order to avoid complication of control circuits and wiring for performing this purpose. [Means for Solving the Problems] In order to achieve the above object, the semiconductor nonvolatile memory device of the present invention is configured as follows. a first gate electrode having a first conductivity; a second gate electrode having a second conductivity provided insulated from the first gate electrode; and a plurality of layers provided under the first gate electrode. a first insulating film consisting of;
a second insulating film that is at least one layer provided under the second gate electrode and is thicker than any of the films constituting the first insulating film; and the first gate electrode and the second gate electrode. It has a semiconductor region provided through a first insulating film and a second insulating film. A memory transistor having the first gate electrode as a gate electrode, and a memory transistor having the second gate electrode on both sides thereof.
A pair of address transistors having a common gate electrode are formed. Note that the first insulating film is preferably formed of a silicon oxide film, a silicon nitride film on the silicon oxide film, and a silicon oxide film on the silicon nitride film. The first gate electrode may be formed of an insulating film consisting of a silicon oxide film, a silicon nitride film on the silicon oxide film, and a silicon oxide film on the silicon nitride film, or a second gate electrode made of an insulator. It is preferable to insulate it from the gate electrode. Alternatively, the first gate electrode is separated from the second gate electrode by an insulating film consisting of an oxynitride film, a silicon nitride film on the oxynitride film, and a silicon oxide film on the silicon nitride film. It may be insulated. Then, it is preferable to connect the first gate electrodes of a large number of memory cells to a write line so that all the first gate electrodes are connected by the write line. Furthermore, the method for writing information into a semiconductor non-volatile memory device according to the present invention is a method for writing information into the semiconductor non-volatile memory device according to the present invention, and in order to achieve the above-mentioned purpose, particularly high-speed writing, at least the following: It has 1 to 3 stages. 1 applying a voltage that induces carriers in the semiconductor region under the first gate electrode to the first gate electrode and the second gate electrode; 2 inducing carriers in the semiconductor region under the first gate electrode; applying a voltage to the first gate electrode to hold the carrier in the semiconductor region under the first gate electrode; 3. applying a voltage to the first gate electrode to hold the carrier in the semiconductor region under the first gate electrode; applying a voltage to be injected into the semiconductor region only to the first gate electrode; and applying a voltage to hold the induced carriers in the semiconductor region under the first gate electrode; The voltage should be lower than the voltage injected into the insulating film. [Function] The semiconductor nonvolatile memory device of the present invention constitutes one memory cell by a memory transistor and a pair of address transistors, but there is no need to provide an impurity layer between the source and drain, and the process of manufacturing is simple. Since the redundancy in the overlay accuracy is reduced, and the gate electrodes of the pair of address transistors are one common electrode (second gate electrode),
The memory cell area can be miniaturized, and a highly integrated, large-capacity semiconductor nonvolatile memory device can be realized. Furthermore, the first insulating film under the first gate electrode of the memory transistor is composed of multiple layers, and the insulating film under the second gate electrode of the address transistor is thicker than any of the films constituting the first insulating film. It also has sufficient voltage resistance. Furthermore, each memory cell can be erased, written, and
In the case of reading, it is sufficient to control the first and second gate electrodes, so that a large capacity can be achieved without complicating the control circuit or wiring. Furthermore, by implementing the writing method for a semiconductor nonvolatile memory device according to the present invention, high-speed writing becomes possible. That is, conventional writing of information into this type of semiconductor nonvolatile memory device is performed by inducing carriers (generally electrons) under the gate electrode of a memory transistor and injecting the induced carriers into an insulating film. This induction and injection of carriers is performed continuously by applying voltage to the gate electrode of the memory transistor and the gate electrode of one of the address transistors for each memory cell, and it takes about 10 milliseconds. It took a considerable amount of time to write information into memory cells. In contrast, the write method according to the present invention induces carriers in the semiconductor region under the gate electrode of the memory transistor of each memory cell, and then retains the carriers in the semiconductor region under the first gate electrode. For memory cells all the first
After carriers are held in the semiconductor region under the gate electrode of each memory cell, a voltage is applied to all the first gate electrodes to inject the held carriers into the first insulating film. Carrier injection can be performed. It takes only a few nanoseconds to induce and hold carriers in the semiconductor region under the gate electrode of a memory transistor, so even if there are a large number of memory cells, the time required for this is small; By completing the step of injecting carriers into the insulating film only once, it is possible to significantly shorten the writing time. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1a shows a first embodiment of the semiconductor nonvolatile memory device of the present invention. Impurity layers 4 and 5 are formed on the surface of semiconductor region 10 on silicon substrate 11 with a predetermined interval.
Furthermore, a gate insulating film C of an address transistor is provided in contact with the channel region between impurity layer 4 and impurity layer 5. This gate insulating film C is composed of a silicon oxide film. A part of the gate insulating film C on the channel region is opened, and the gate insulating film C is formed on the exposed surface of the semiconductor region 10 on the silicon substrate 11.
A silicon oxide film D having a thinner thickness is formed. Furthermore, on top of the gate insulating film C and silicon oxide film D, a silicon nitride film B and a silicon oxide film F, both of which are thinner than the gate insulating film C, are formed. Further, a gate electrode G of the memory transistor, which is a first gate electrode, is provided on the silicon oxide film F so as not to overlap the impurity layers 4 and 5. Furthermore, a common gate electrode I of the pair of address transistors, which is a second gate electrode, is formed on the gate electrode G via an insulator H so as to reach from the upper part of the impurity layer 4 to the upper part of the impurity layer 5. do. That is, in the semiconductor nonvolatile memory device of this embodiment, on the gate electrode G of the memory transistor,
Common gate electrode I of a pair of address transistors formed on both sides of the memory transistor
are overlapped with each other with an insulator H interposed therebetween. Therefore, the impurity layer between the memory transistor and the address transistor, which was conventionally necessary, becomes unnecessary. Therefore, the impurity layer between the memory transistor and the address transistor, which was conventionally necessary, is no longer necessary. The gate electrode I of the address transistor and the gate electrode G of the memory transistor are made of conductive materials having different conductivities. FIG. 1b shows a second embodiment of the semiconductor nonvolatile memory device of the present invention. On the surface of the semiconductor region 10 of the silicon substrate 11,
Impurity layers 6 and 7 are formed with a predetermined interval.
Further, on the channel region between the impurity layers 6 and 7, a silicon oxide film J, a silicon nitride film K, and a silicon oxide film L are formed so as not to overlap the impurity layers 6 and 7.
A memory transistor is provided in which a gate electrode M and a gate electrode M are sequentially stacked. Further, on the gate electrode (first gate electrode) M of this memory transistor, a common gate electrode (second gate electrode) O of a pair of address transistors formed on both sides of the memory transistor is connected to the gate insulator. It is provided to cover the top of the gate electrode M from the top of the impurity layer 6 and reach the top of the impurity layer 7 via the film N. That is, in this embodiment as well, the common gate electrode O of a pair of address transistors formed on both sides of the memory transistor overlaps on the gate electrode M of the memory transistor with the insulating film N interposed therebetween. FIG. 1c shows a third embodiment of the semiconductor nonvolatile memory device of the present invention. A common gate electrode (second gate electrode) of a pair of address transistors via a gate insulating film P
Set up Q. so that it partially overlaps with the gate electrode Q,
Impurity layers 8 and 9 are provided in a semiconductor region 10 of a silicon substrate 11. A part of the channel region between the impurity layers 8 and 9 is opened to expose the semiconductor region 10, and the silicon oxide film R, the silicon nitride film S, the silicon oxide film T, and the second gate electrode U are formed. are stacked in order to form a memory transistor. In the semiconductor nonvolatile memory device shown in FIG. 1c, a common gate electrode Q of a pair of address transistors and a gate electrode U of a memory transistor
are arranged so as to overlap with each other with an insulating film interposed therebetween. In the embodiment described above using FIGS. 1a to 1c, the region forming the channel of the transistor is
Although the semiconductor region 10 on the silicon substrate 11 was explained, the semiconductor non-volatile film of the present invention can also be applied to the surface region of the semiconductor substrate, a separated region on the semiconductor substrate, and a semiconductor thin film formed on a different substrate such as an SOS substrate. Sexual memory can be formed. Furthermore, in the above embodiment, the gate insulating film of the memory transistor was composed of three layers: a silicon oxide film, a silicon nitride film, and a silicon oxide film. A laminated structure of the formed silicon nitride film and a silicon nitride film obtained by directly nitriding the silicon substrate may be used, and a silicon oxide film may be further formed from the gate electrode side.
A stacked structure of a silicon nitride film formed by chemical vapor deposition and an oxynitride film may also be used. Furthermore, the gate insulating film of the memory transistor is
A two-layer structure of a silicon nitride film and a silicon oxide film may be used. In particular, in the embodiment shown in FIG. 1c, the gate insulating film of the memory transistor is formed in a later step than the gate insulating film of the address transistor.
Therefore, there are few chances that the insulating film of the memory transistor, such as a silicon nitride film, is exposed to high temperatures, and good memory characteristics can be achieved with the two-layer structure. Furthermore, since the gate electrode of the address transistor and the gate electrode of the memory transistor can be insulated and separated by a three-layer insulating film consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film, leakage current between the two gate electrodes is reduced. It is possible to suppress the occurrence of and improve the withstand voltage. Further, the impurity layers 4 to 9 are regions into which impurities of conductivity type opposite to the semiconductor region 10 are introduced.
A PN junction may be formed with the semiconductor region 10, or a region such as a metal or silicide layer may be used to form a rectifying junction with the semiconductor region 10. If the semiconductor region 10 is a thin film, it can be replaced with a low resistance region having ohmic contact with the semiconductor region 11. The region between these impurity layers and the channel region of this impurity layer is used for reading and writing information, and thus becomes a reading and writing region. Next, the writing method of the semiconductor non-volatile memory device according to the present invention will be explained using the structure shown in FIG. 1b as an example.
This will be explained using FIG. FIG. 3 shows the structure of a memory matrix using the semiconductor non-volatile memory device of the present invention, in which the shaded areas are memory transistors and the black circles are electrical contacts. As shown in FIG. 3, impurity layers 6 and 7 are connected to data lines D ₁ , D ₂ , D ₃ and D ₄ , respectively. Furthermore, a common gate electrode O of a pair of address transistors
are connected to address lines A ₁ and A ₂ respectively. The gate electrode M of the memory transistor is connected to the write line W.
Furthermore, all gate electrodes M are connected to one write line W. For example, as shown in FIG. 3, in a memory matrix configuration of 2 rows and 2 columns, information "1" is stored at addresses (1, 1) and (2, 2). 1) Let us consider the case where information "0" is written to address. Here, the state of information "1" refers to a state in which electrons are trapped in the silicon nitride film constituting the gate insulating film of the memory transistor. Table 1 shown on the next page shows data lines D ₁ , D ₂ , D ₃ ,
D ₄ , address lines A ₁ , A ₂ , and write line W;
The relationship between the applied bias voltages is shown. Note that the magnitude relationship of each bias voltage of HW, H, L, and LW in Table 1 is HW>H>L>LW.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
The impurity layer required in conventional memory cells becomes unnecessary. Furthermore, redundant overlay accuracy required when manufacturing semiconductor nonvolatile memory devices is also reduced. Therefore, a significant reduction in memory cell area can be achieved. Furthermore, even if a high voltage is applied to the drain region during information writing, the ultra-thin gate insulating film of the memory transistor is sufficiently thicker than the gate insulating film of the address transistor. Since it is insulated from the drain region, the withstand voltage against dielectric breakdown can be significantly improved. Furthermore, each memory cell can be erased, written, and
When reading data, it is sufficient to control only two gate electrodes, the first and second, so that a large capacity can be achieved without complicating the control circuit or wiring. Further, according to the method for writing in a semiconductor nonvolatile memory device according to the present invention, the time required to write information can be significantly shortened and high-speed writing can be performed. In other words, the time required for each step shown in Table 1 is from several nanoseconds to several tens of nanoseconds from the stage of holding electrons only under the gate insulating film of the memory transistor at the address where information is written, to the time required for batch erasing. The phase and writing phase each last from a few milliseconds to several tens of milliseconds. Therefore, for example,
In the case of a memory matrix with 8 kilo bits of address line, when 8 bits of memory is connected to one address line, at 64 kilo bits,
Assuming that the steps from Table 1 are 10 nanoseconds and each step is 10 milliseconds, then 10×10 ^-9 ×8×10 ³ +10×10 ^-3 ×2 = 2.0×10 ^-2
[seconds]. On the other hand, in the conventional writing method, 1
Each address line requires a write time of 10 milliseconds. For the same 8 km address line as above, it will take 10 x 10 ^-3 + 10 x 10 ^-3 x 8 x 10 ³ = 80 [seconds]. Therefore, it can be seen that the writing method according to the present invention is more effective as the capacity of the memory increases.

[Brief explanation of the drawing]

1a, 1b, and 1c are all cross-sectional views showing a semiconductor nonvolatile memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional memory cell, and FIG. 3 is a cross-sectional view showing a conventional memory cell. FIG. 2 is a circuit diagram showing a memory matrix using the semiconductor nonvolatile memory device of the present invention. 4, 5, 6, 7, 8, 9... impurity layer, 10...
...semiconductor region, C, N, P...gate insulating film,
D, J, R...silicon oxide film, E, K, S...
Silicon nitride film, F, L, T... silicon oxide film, G, M, U... gate electrode, H... insulator,
I, O, Q...gate electrode, _A1 , _A2 ...address line, _D1 , _D2 , _D3 , _D4 ...data line, W...write line.

Claims (1)

[Claims] 1. A first gate electrode having a first conductivity;
a second gate electrode having a second conductivity provided insulated from the first gate electrode; a first insulating film consisting of a plurality of layers provided under the first gate electrode; and the second gate electrode. a second insulating film that is at least one layer provided under the electrode and is thicker than any film constituting the first insulating film; and the first gate electrode and the second gate electrode are connected to the first insulating film. a semiconductor region provided through a film and a second insulating film, the memory transistor having the first gate electrode as a gate electrode, and the second gate electrode on both sides thereof as a common gate electrode. 1. A semiconductor nonvolatile memory device comprising a pair of address transistors. 2. The method according to claim 1, wherein the first insulating film is composed of a silicon oxide film, a silicon nitride film on the silicon oxide film, and a silicon oxide film on the silicon nitride film. Semiconductor non-volatile memory device. 3. The first gate electrode is an insulating film consisting of a silicon oxide film, a silicon nitride film on the silicon oxide film, and a silicon oxide film on the silicon nitride film, or the second gate electrode is made of an insulator. 2. The semiconductor nonvolatile memory device according to claim 1, wherein the semiconductor nonvolatile memory device is insulated from the semiconductor nonvolatile memory device. 4 The first gate electrode is insulated from the second gate electrode by an insulating film consisting of an oxynitride film, a silicon nitride film on the oxynitride film, and a silicon oxide film on the silicon nitride film. A semiconductor nonvolatile memory device according to claim 1, characterized in that: 5. The semiconductor nonvolatile memory device according to claim 1, wherein the first gate electrode is connected to a write line, and all the first gate electrodes are connected by the write line. 6 a first gate electrode having a first conductivity;
a second gate electrode having a second conductivity provided insulated from the first gate electrode; a first insulating film consisting of a plurality of layers provided under the first gate electrode; and the second gate electrode. a second insulating film that is at least one layer provided under the electrode and is thicker than any film constituting the first insulating film; and the first gate electrode and the second gate electrode are connected to the first insulating film. a semiconductor region provided through a film and a second insulating film, the memory transistor having the first gate electrode as a gate electrode, and the second gate electrode on both sides thereof as a common gate electrode. A method of writing information to a semiconductor nonvolatile memory device formed with a pair of address transistors, the method comprising: applying a voltage that induces carriers in a semiconductor region under the first gate electrode to the first gate electrode and the second gate electrode; applying a voltage to the first gate electrode to maintain carriers induced in the semiconductor region under the first gate electrode in the semiconductor region under the first gate electrode; applying a voltage only to the first gate electrode to inject carriers held in the semiconductor region under the first gate electrode into the first insulating film, and injecting the induced carriers into the first insulating film. A method for writing in a semiconductor nonvolatile memory device, characterized in that a voltage held in a semiconductor region under a first gate electrode is lower than a voltage at which the held carriers are injected into the first insulating film.