JPH0277169A - non-volatile memory device - Google Patents

Abstract

PURPOSE:To make possible the electrical erase of one transistor/cell by a method wherein this device is provided with second insulating films formed thinly on the sidewalls of first gate electrodes and a third electrode formed inserting these second insulating films between the first gate electrodes and the third electrode. CONSTITUTION:Tunnel oxide films 6a and 6b are formed on the respective sidewalls of floating gate electrodes 5a and 5b on the side of a source diffused layer 2 and an erase gate electrode 7 is formed being inserted between the electrodes 5a and 5b. The electrode 7 is electrically connected to the layer 2 so as to work as a source electrode as well. Control gate electrodes 9a and 9b are respectively formed on the electrodes 5a and 5b through insulating films 8a and 8b. Moreover, CVD oxide films 10a and 10b are respectively formed in such a way as to cover these electrodes 5a and 9a and 5b and 9b. As a necessary potential is given to the electrode 7 and a charge can be taken out from the electrodes 5a and 5b to the electrode 7 through the films 6a and 6b, a rewriting becomes electrically possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile memory device having an electrically rewritable gate electrode structure of two or more layers.

(Prior art) In recent years, ultraviolet erasable EFRO has been used as a nonvolatile memory device.
Batch erase type EEP of 1 transistor/cell instead of M
ROM is attracting attention. So this - Batch elimination type EEF
As an example of a ROM, one having a two-layer polycrystalline silicon gate structure is shown in FIG.

A source diffusion layer 22 and a drain diffusion layer 23 are formed in a p-type silicon substrate 21.

The junction depth of the source diffusion layer 22 is set to be deep enough so that the junction breakdown voltage is greater than the erase voltage. Also,
A gate oxide film 24 is formed on the p-type silicon substrate 21 between the source diffusion layer 22 and the drain diffusion layer 23. A floating gate electrode 25 is formed on this gate oxide film 24. A control gate electrode 27 is formed on this floating gate electrode 25 with an insulating film 26 interposed therebetween.

The operating mechanism of this batch erase type EEFROM is as follows. Information is written by applying a high voltage to the control gate 27 and drain diffusion layer 23 and injecting channel thermoelectrons into the floating gate electrode 25 and accumulating them to increase the threshold of the cell transistor, similar to the ultraviolet erasable EPROM. This is done by letting Information can be erased by applying an erase voltage to the source diffusion layer 22 and applying zero potential to the control gate electrode 27 to cause a tunneling current to flow through the gate oxide film 24, thereby transferring accumulated electrons to the floating gate electrode 2.
5 to the source diffusion layer 22.

Such a bulk erase type EEFROM has a source diffusion layer 2
2 is shared in the array, erasing is performed at once, and as a result, the cell area is almost the same as that of an ultraviolet erasable EFROM.

However, if the erase voltage is set to a practical value, e.g.
．． In order to set the voltage to 5 [V], it is necessary to reduce the thickness of the gate oxide film 24 by about 100 layers. Therefore, there is a drawback that defects in the gate oxide film 24 increase and yield deteriorates. Furthermore, as the surface breakdown voltage of the source junction decreases due to the thinning of the gate oxide film, junction leakage currents coexist in addition to F and N tunnel currents when erasing information. This has disadvantages in that stable operation of the memory cell is inhibited and it is impossible to realize single 5 [V] power supply operation.

(Problems to be Solved by the Invention) As described above, in the conventional nonvolatile memory device, since a thin gate oxide film had to be used, there was a drawback that the reliability of the memory cell could not be sufficiently increased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an electrically erasable nonvolatile memory device having one transistor/cell and having reliability comparable to that of an ultraviolet erasable EPROM.

[Structure of the Invention] (Means for Solving the Problems and Their Effects) In order to achieve the above object, the nonvolatile memory device of the present invention includes a first region and a second region formed in a surface region of a semiconductor substrate. a first gate electrode formed on the channel region between the first region and the second region and placed in an electrically floating state; and a first insulating film on the first gate electrode. In a non-volatile memory device in which a memory cell is a transistor having a second gate electrode formed through the first gate electrode and a second gate electrode serving as a control gate, the second gate electrode is formed thinly on the side wall of the first gate electrode. A second insulating film and a third electrode formed by interposing this second insulating film with the first gate electrode are provided. As a mechanism for the erasing operation, a necessary potential is applied to the third electrode and the first
The charge stored in the gate electrode is extracted to the third electrode through the second insulating film.

According to such a non-volatile memory device, electrical rewriting becomes possible and the first insulating film does not need to be thinned in order to improve erasing characteristics.

Therefore, it is possible to provide a 1 transistor/cell electrically erasable nonvolatile memory device that has higher reliability than a nonvolatile memory device in which the first insulating film must be formed thin.

Furthermore, if the second insulating film is a polycrystalline silicon oxide film, a good oxide film can be formed on the sidewall of the first gate electrode by performing heat treatment.

(Example) Hereinafter, a first example of the present invention will be described in detail with reference to FIG.

FIG. 1 shows the nonvolatile memory device of this embodiment. This nonvolatile memory device has a p-type silicon base If
A source diffusion layer 2 and drain diffusion layers 3a and 3b of the memory cell are formed in the surface region f. Gate oxide films 4a and 4b are formed on the channel region between the source diffusion layer 2 and drain diffusion layers 3a and 3b. Floating gate electrodes 5a, 5b are formed on gate oxide films 4a, 4b. On the side walls of these floating gate electrodes 5a and 5b, a tunnel oxide film 6a is formed on the side of the source diffusion layer 2.
, 6b are formed. These tunnel oxide films 6a, 6
b is the floating gate electrode 5a.

An erase gate electrode 7 is formed sandwiched between the electrode 5b and the electrode 5b. This erase gate electrode 7 is common to the memory cells in the array and is electrically connected to the source diffusion layer 2 so as to also function as a source electrode. Control gate electrodes 9a and 9b are formed on the floating gate electrodes 5a and 5b with insulating films 3a and 3b interposed therebetween. Further, CVD oxide films IQa, 10b are formed to cover these floating gate electrodes 5a, 5b and control gate electrodes 9a, 9b.

Furthermore, a BPSG film 11 is formed on the entire surface, and this BPS
G film 11 film type 1 drain diffusion layer 3a.

A contact hole is provided on 3b. A bit line 12 is formed to be electrically connected to the drain diffusion layer 3a through a contact hole provided on the drain diffusion layer 3a.

Such a nonvolatile memory device can be electrically rewritten because a necessary potential can be applied to the erase gate electrode and charges can be extracted from the floating gate to the erase gate through the tunnel oxide film. As an example of the method for manufacturing the nonvolatile memory device, first, a two-layer polycrystalline silicon gate electrode is formed in the same manner as in the conventional batch erasing type EEPROM shown in FIG. After this, a thin insulating film is applied only to the side walls of the floating gate electrode, e.g.
A polycrystalline silicon oxide film with a thickness of about 00λ is formed.

Next, after a contact hole is opened in the insulating film on the source diffusion layer, polycrystalline silicon doped with n-type impurities is deposited over the entire surface. Then, this polycrystalline silicon is patterned so that it remains across the two word lines, and an erase gate electrode (source electrode) electrically connected to the source diffusion layer is formed.

According to this structure, since the erase gate electrode is formed on the side wall of the floating gate electrode via the tunnel oxide film, the tunnel oxide film and the gate oxide film can be formed separately. Therefore, the tunnel oxide film can be optimized depending on the erase voltage.

Further, since the gate oxide film does not need to be made thinner in order to improve erase characteristics, the source junction breakdown voltage can be sufficiently increased.

Note that in the above embodiment, the erase gate electrode electrically connected to the source diffusion layer was formed on the source diffusion layer, but the erase gate electrode electrically connected to the drain diffusion layer was formed on the drain diffusion layer. It's okay. In this case, the tunnel oxide film on the side wall of the floating gate electrode is preferably provided on the drain diffusion layer side.

Furthermore, the tunnel oxide film may be provided over the other side surface of the floating gate electrode.

A second embodiment of the present invention will be described in detail below with reference to FIG.

FIG. 2 shows the nonvolatile memory device of this embodiment. This nonvolatile memory device consists of a p-type silicon substrate 1
A drain diffusion layer 102 and a source diffusion layer 103a of the memory cell are formed on the surface of 01.

103b is formed. These are drain diffusion layer 1
02 and a gate oxide film 104a on the channel region between the source diffusion layers 103a and 103b.

104b is formed. This gate oxide film 104a
, 104b are formed with floating gate electrodes 105a and 105b. This floating gate electrode 105a.

On the sidewall of 105b, tunnel oxide films 106a and 106b are formed on the drain diffusion layer 102 side. This tunnel oxide film 106a.

An erase gate electrode 107 is formed by sandwiching the electrode 106b between the floating gate electrodes IQ5a and 105b. This erase gate electrode 107 is electrically connected to the drain diffusion layer 102 so as to function as a drain electrode.

Insulating film 10 on the floating gate electrodes 105a and 105b
8a, 108b and source regions 103a, 103b
Insulating film 104a.

Control gate electrodes 109a and 109b are formed on 104b so as to have an offset structure.

Further, CVD oxide films 110a and 110b are formed to cover these floating gate electrodes 105a and 105b and control gate electrodes 109a and 109b. Furthermore, B on the entire surface
A PSG film 111 is formed, and a contact hole is provided in this BPSG film 111 above the drain diffusion layer 102.

The bit line 112 connects to the drain diffusion layer 1 through a contact hole provided on the drain diffusion layer 102.
02.

In such a nonvolatile memory device, as in the first embodiment, electric charges can be extracted from the floating gate to the erase gate through the tunnel oxide film by applying a necessary potential to the erase gate electrode, so that electrical rewriting can be performed. is possible.

According to such a configuration, the floating gate electrodes 105a, 1
Since the erase gate electrode is formed on the side wall of the tunnel oxide film 106a and 106a through the tunnel oxide film,
06b and gate oxide films 104a and 104b can be formed separately. Therefore, the tunnel oxide film 106a,
106b can be optimized depending on the erase voltage. Further, since the gate oxide films 104a and 104b do not need to be made thinner in order to improve erase characteristics, the drain junction breakdown voltage can be sufficiently increased.

Moreover, in this embodiment, the source diffusion layer 10aa.

The control gate electrode 109a is located above the source diffusion layer on the channel between the drain diffusion layer 103b and the drain diffusion layer 102.

109b is formed in an offset structure. This causes floating gate electrode 105a.

Even if too much charge is extracted (overlay) during the gap in which charges are extracted from the erase gate electrode 105b to the erase gate electrode 107, the presence of the control gate electrode on the channel prevents the channel from becoming electrically conductive.

Furthermore, the tunnel oxide films 106a and 106b may be provided across the other side surfaces of the floating gate electrodes 105a and 105b.

[Effects of the Invention] As described above, the nonvolatile memory device of the present invention provides the following effects.

It is possible to obtain a reliability comparable to that of an ultraviolet erasable EP ROM, and to provide an electrically erasable nonvolatile memory device with one transistor/cell.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining a nonvolatile memory device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a memory device according to a second embodiment of the present invention. , FIG. 3 is a cross-sectional view for explaining a conventional nonvolatile memory device. 2... Source diffusion layer. 3a, 3b...Drain diffusion layer, 4a, 4b.
... Gate oxide film, 5a, 5b ... Floating gate electrode, 15a, 5b ... Tunnel oxide film, 7 ... Erase gate electrode (drain electrode), 9
a, 9b... Control gate electrode.

Claims (4)

[Claims] (1) A first region and a second region formed on the surface region of the semiconductor substrate, and a channel region formed between the first region and the second region and placed in an electrically floating state. In a nonvolatile memory device in which a memory cell is a transistor having a first gate electrode and a second gate electrode formed on the first gate electrode via a first insulating film and serving as a control gate, A second insulating film is formed on the side wall of the first gate electrode, and the second insulating film is sandwiched between the first gate electrode and the first region or the first gate electrode. 1. A nonvolatile memory device comprising: a third electrode electrically connected to either one of the second regions. (2) A first region and a second region formed on a surface region of a semiconductor substrate, and a channel region formed on a channel region in contact with the first region between these first region and second region, and electrically conductive. A first gate electrode is formed in a floating state, and a substrate insulating film is formed on a first insulating film formed on the first gate electrode and on a channel region in contact with a second region. and a second insulating film formed on a side wall of the first gate electrode on the first region side; , a third electrode formed by sandwiching the second insulating film with the first gate electrode and electrically connected to the first region. memory device. (3) Applying a necessary potential to the third electrode,
3. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory device is electrically rewritten by extracting the charge stored in the gate electrode through the second insulating film to the third electrode. (4) The nonvolatile memory device according to claim 1, wherein the second insulating film is a polycrystalline silicon oxide film.