JPS58147154A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To enable highly reliable writing and erasing operations by completely surrounding an impurity region of rewriting region with a field insulating film, conducting it with a crossunder diffused layer to hold the same potential, thereby preventing the deterioration in the characteristics of the informing rewriting region. CONSTITUTION:An n<+> type layer 23 held at the same potential as a source 22 is formed adjacent to a channel region, and a floating gate 25 is extended on the region. The second control gate 31 made of polycrystalline silicon or metal which is capacitively coupled to the gate 25 is formed by insulating them via gate insulating film 26, 30 separately from the first control gate 27. The periphery of a gate insulating film 29 on an n<+> type layer 28 of rewriting region is surrounded by a completely thick field insulating film 32. This layer 28 is conductecd with the source 22 via an n<+> type crossunder diffused layer 33 formed in advance under the layer 32.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to floating? -) and control darts integrated in a matrix on a semiconductor substrate, particularly a nonvolatile semiconductor memory device that can be electrically and selectively rewritten. Regarding.

[Technical background of the invention and points of interest]

Conventionally, a non-volatile semiconductor memory device having a floating r-) is constructed of an MO8 type field effect transistor having a floating r-t electrically insulated from others and a control r-) above it. In a memory device having multiple storage capacities, the memory elements are arranged in a matrix, control darts are commonly connected in each row to form a word line, drains are connected in common in each column, and transistors are connected in common in each row. It is composed of lines.

FIG. 1 shows the structure of a conventionally used non-volatile medium conductor memory element for detecting floating ff-. @l
1l(a) is a plan view, and the A''A'''A' cross section is the same (ml-1' cross section).Basically,
This is a Mol type field effect transistor having an insulated floating dart 16 and a control dart 1F. 11 is p tI
IB quantity substrate, 12 and 13 are mNO source and drain, 14 and 15 are insulators, and IJ is a field insulating film. Write control r-) 1
A high voltage is applied to F and the drain 13, and hot electrons generated near the drain are injected into the floating r-t 16 by K. Hideshisha conducts this by applying an appropriate potential to the control r-to-IT and the drain 13, and detecting whether or not a current flows between the drain 13 and the source 12 depending on whether or not charge is injected into the floating dart 16. be exposed. For example, the floating r-t 16 can be erased by irradiating it with ultraviolet rays.
This is done by discharging a large charge accumulated in K.

In the structure shown in JillN, ultraviolet light or the like must be used to erase information as described above, and in this case, all memory elements arranged in a matrix must be erased at the same time, and selective erasure is not possible. There was a drawback.

[Purpose of the invention]

In the present invention, non-volatile conductor memory elements having floating r-) and control 41 darts are arranged in a matrix, and information is electrically and selectively written in a rewrite area provided separately from the channel area of the element. An object of the present invention is to provide a nonvolatile conductor memory device that is replaceable.

Another object of the present invention is to provide a non-volatile conductor memory device which prevents the deterioration of the characteristics of the information rewrite area of the memory element as described above and enables highly reliable write and erase operations.

[Summary of the invention]

The present invention uses a structure in which a region for selective programming and erasing is provided separately from the channel region as a nonvolatile conductor memory element. That is, the source t of the memory element is in the substrate.
An impurity region of the same conductivity type for information writing is provided near the t and rain, and a floating f which continues from above the channel region through a dart extension is formed on this impurity region.
-), and furthermore, first and 1s20 manufactured darts are provided so as to capacitively couple to this floating ff-). As such a structure, the above jll.

Second control? -) and the impurity region by selecting the potential relationship between the impurity region and the floating r-) above it, transfer of charge by a tunnel current. Selecting a 1-element/cell memory cell array. The basic idea is that it can be rewritten 19 times.

1+ In the basic structure as described above, the present invention completely replaces the impurity region of the replacement region with a field insulating film*! It is characterized in that the impurity region and the source or drain are electrically connected to each other by a so-called four-sunder diffusion layer formed under a field insulating film to maintain the same potential.

〔Effect of the invention〕

According to the present invention, a non-volatile semiconductor memory device can be obtained in which information is electrically and selectively rewritten as ``IME'' in the tX element/cell configuration. The f, -) insulating layer is completely surrounded by a thick field insulating film, so that it is difficult for local electric field concentration to occur in the e -t insulating film during rounding, writing, and erasing, and therefore, the field C) I' -) Since a tunnel current flows across the entire surface of the insulating material, a highly reliable memory device with little deterioration of the dirt insulating film even after repeated writing and erasing is congratulated.

[Embodiments of the invention]

FIG. 2 shows the main structure of a memory element according to an embodiment of the present invention, in which (a) is a plan view, Cb) Ct) and (d)
are respectively −) moum/ , B −ml and c
-c' cross section. For p-type Sl substrate 21! A Kr gate edge 1 is provided on the channel region between these two regions, and a floating dart 25 made of polycrystalline silicon is provided via a dirt insulator M24.
1 [1st CI control r-)2F made of polycrystalline silicon via JJ The basic structure is the same as before. In addition to the basic structure described above, this embodiment provides a separate area for writing and erasing information. That is, the 11M layer 18 maintained at the same potential as the source 22 is provided in contact with the channel region K11l, and the floating layer 18 is placed on the layer 2# with a thin r-) insulating layer 29 interposed therebetween. -) Extend J 6. And apart from the 1st C) control r-) J F? −) Floating r −) J
A control layer (JJ) made of polycrystalline silicon or metal that capacitively couples to the L is provided.・What is important here is that, as is clear from -), (@) and (41), the r-) insulating film 29 on the mllll layer 28, which is the rewriting area, is a completely thick field insulator of 70Sm. membrane 12
It means that it is surrounded by a bank. And this Owa+
Lid layer 1g111 field insulation l[9-/shoulder 7under diffusion layer JJ formed in advance under JJ to source j2
K is set so that it conducts with.

The insulators M24*2ik and 30 are, for example, thermal oxide films with a thickness of about 600×, and the r-) insulating layer 29 in the area where writing and erasing operations are performed has a film thickness of, for example, 200×, which is sufficient to cause a tunnel effect. A thermal oxidation layer of @degree. In addition, when configuring an array by arranging these elements in a matrix, the source 22 and the first control f-) Jr are common in the row direction, and the second control 11f-g and 31 are omitted from the figure. The drain electrode wiring is commonly arranged in the column direction.

Next, the operation of this memory element will be explained. A drain potential v1, a source potential v, a substrate potential v, 11, a first oflJ@f-to potential vc, 1, and a second control potential VCG2 are applied to this memory element from the outside. This memory element is shown in the price circuit in Figure 3, so it is a floating goo.)
The potential V of Jj. L is generally expressed by the following formula.

However, Cc and t ” cyl are respectively 1.ji2
The total capacitance i%C, #C□, , C1 between the control r-t 2F, 11 and the floating r-t −)
It has a total capacity of 710 cm.

CCFI and C (!Fj are approximately equal, C, /ri are set smaller). From the above equation, if drain potential v1, substrate potential V□1, and source potential V are fixed, floating using %111 control r-) J r and @20 control r-) J 1? - It can be seen that the 2150 potential level has three states. That is, (1) the first control gate sr
and the second control r-) J1 are both at high potential, (1)
No. xolJ control r-) 2F, 31g+2) control r-t J1
If one of them is at a high potential and the other is at a low potential, (MI
When the control r-t xr of DIll and the second control @l'-) 31 are both at low potential, the floating r-) J
The potential of J is determined. Therefore, only when the source potential V is in the (:) state and the source potential V is a low potential, and only when the source potential V1 is in the - state and the source potential V1 is a high potential, the ? -) Selective writing or erasing can be performed in this region by selecting the thickness of the insulating film 29 so that a tunnel current flows through the insulating gxe and does not flow in other states.

In reality, the memory elements shown in FIG. 2 are integrated and formed in a matrix on a substrate to form a one-layer/cell memory array as described above. For example, as shown in figure j14, 49M
Consider a matrix of memory elements M, .about.M4. Ml
North 8□ of and M is common, source gm of Ms and K4
4 are common. Similarly $1 (D control goo) CG, 1[
M.

Common to M, the first CI control f-) CG, is M.

It is common to M.

Also the drain D, and the second control f-) CG, 1 is M
, , M, common to dray 7D, and second control l'-
)CG*m is common to Kga K4. In the initial state, no charge is accumulated in the floating r-t of each memory element, and this state is assumed to be @1m, for example. To write data to the memory capacitor M, apply +20V to the first control @r)CGII and the second control @P-)CG, and connect all other terminals and the wholesale drain DB. e DB, source B1
m8m, #1O control l')CGi*, second control r
)CGIItiOV. In this way, the memory elements M, O (floating) 71 will have a temporary potential, and the iris 1. j1
2C) Control P) CGll a CG□.

Intersecting region C) r-) n+ type layer 2 through insulating film 2-
1 to 21FC.

This is K] The threshold value of the memory element M1 moves in the positive direction and becomes a write state g@o''.

Next, when erasing the contents of memory element M1, apply IK+20 V to source 8s -11m, train I)t+I)* open & (+20V), and ll1
1 control? ”-)CG■ and the second control goo)CG□Q
V, the first control 'r'-)CGIm and the second control r-toCG■ are set to +20V. This is K), the printing element M1
Only that floating r-) 25 becomes a low potential, floating r-)
The electrons accumulated in J l are emitted to the t-type layer 28, that is, the source, by the tunnel current, resulting in an erased state 1.
Return to a1@1” state.

When reading the contents of the memory element M1, the drain Ds
K read potential (e.g. +5v), first control 'l'
) Apply a selection potential (for example, +6V) to CG is, and set everything else to 0■. Accordingly, when the memory element M1 is @son1, a channel current flows, and when it is "1#", no channel current flows, so ``1'',
``0'' can be determined.

Thus, according to this embodiment, a memory device is obtained in which a scanning information rewriting region is provided using the tunnel effect separately from the channel region of the element, thereby enabling electrical and selective writing and erasing.

According to this embodiment, since the periphery of the rewriting area is completely surrounded by the field insulating film, local electric field concentration occurs in the r-) insulating film in that area. r-) A highly reliable non-volatile memory whose writing and erasing characteristics do not deteriorate even after multiple information rewriting operations by ensuring that a uniform tunneling current flows throughout the entire area of the insulating film. will be realized.

The memory element shown in Figure 2 is the first memory element. Control of irises '2? ”−
Floating with Tosr Italy J1? −) Coupling capacitance CC with J j
F1 a Ccy2 Fi is approximately equal to n+ type layer 28 (
That is, the coupling capacitance C between the source 22) and the floating r-) j j is configured to be smaller than this.

A higher operating margin than K can be obtained. That is, CCF
l# This is because if the variation Ii of CCF2 is large, the on/off ratio becomes small, and if the error C1 becomes large, this also results in a reduction in the on/off ratio.

Note that the present invention is not limited to the above embodiments. For example, for a write operation, a method of injecting hot electrons from a channel region can be used as in the conventional method. The source and P-rain of the memory element may be considered in the opposite manner to the above embodiment, or a p-channel memory element may be used.

[Brief explanation of the drawing]

Figures 1g1-) to (・) are diagrams showing the structure of the main parts of conventional nonvolatile memory elements, and Figures 2 (,) to (d) are the W
A diagram showing the main structure of a memory element in one embodiment of #
Figure I3 is an equivalent circuit diagram of the memory element, and Figure 4 is an equivalent circuit diagram of the memory element 7. It is a diagram illustrating mourning by arranging them in a matrix. 21-p type St substrate, 22-np north, 23・-1+
type drain, 24.26.19.30-r-t insulating film, 25-floating r-), 2r...first control y-t, 2
g...n-type layer (1! replacement impurity region), 31-2nd
control r-), 32--field insulating film, 33--n
Cross under diffusion layer. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 2 Figure 3 Figure 3 Figure 4

Claims (1)

[Claims] In a device containing a non-volatile semiconductor in which memory elements having floating r-) and wan'-) are integrated on a semiconductor substrate in the form of a box, each memory element is spaced apart over the semiconductor substrate. A large source and a drain are formed, an impurity region of the same conductivity type as the source and drain is provided near the source and the drain, and an impurity region is formed on the impurity region and on the channel region between the source and the drain. Floating r-
) and this floating? -) and a twentieth control gate, the impurity region has an edge M completely surrounded by a thick field insulating film and a field insulating film. A non-volatile conductor metering device, characterized in that it is maintained at the same potential as either the source or the drain by a large cross-under diffusion layer formed under the membrane.