JPS5933881A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable to electrically and selectively rewrite information as an element/cell structure by forming an offset gate structure that a floating gate partly covers a channel region, reading out at least part of the first and second control gates at the remaining part to cover as electrodes. CONSTITUTION:An n<+> type source 22, drain 23 are formed on a p type Si substrate 21, a floating gate 25 made of the first layer polysilicon film is formed through a gate insulated film 24 on a channel region between both regions, and the first and second control gates 27, 28 patterned in the second layer polysilicon film are formed through a gate insulated film 26 thereon. The gate 25 is not covered over the offset gate structure, i.e., the entire channel region for the source 22 and the drain 23, and the remaining part is covered with the first and second control gates 27, 28.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a non-volatile semiconductor memory device in which memory cells having floating dirt and control dirt are integrated in a matrix on a semiconductor substrate, and particularly relates to The present invention relates to a nonvolatile semiconductor memory device that is selectively rewritable.

[Technical background of the invention and its problems]

Conventionally, a non-volatile semiconductor memory device having a floating dart is composed of an electrically insulated floating dart and an MO8m field effect transistor having a control dart on top of the floating dart. A memory device with multiple storage capacities is constructed by arranging the memory elements in a matrix, connecting control gates in common to each row to form word lines, and commonly connecting drains to each column to form bit lines. be done.

FIG. 1 shows the main structure of a conventionally used nonvolatile semiconductor memory device having a floating board. @1 Figure (a) and plan view 1 (b) show the A-A' cross section, and (C) the same <B-B' cross section. Basically, an insulated floating dart 16 and a control dart 1
It is an MO3 type field effect transistor with 7. No. 1 is a pms1 substrate, 12 and 13 are an n-type source and drain, respectively, and 14 and 15 are dirt insulating films. An n+ region 18 adjacent to and connected to the source 12 is provided as a rewriting region, and a floating dart 16 is extended thereon via an extremely thin dart insulating film 19 through which a tunnel current flows.

Writing in this memory requires drain 13 and source 1
2 as a low potential and control gate 17 as a high potential, ? Area 1
This is done by injecting all of the electrons from 8 into the floating gate 16 by means of a tunnel current. Erasing is performed by reversing the potential relationship. Further, reading is performed by applying appropriate potentials to the control gate 17 and the drain 13 and completely detecting whether or not current flows between the drain 13 and the source 12 depending on whether or not charge is injected into the floating gate 16. .

By the way, in the structure shown in Fig. 1, if this element is arranged in a matrix, and for example, the source 12 and the limit are marked, -1 and 17 are commonly connected in the X direction, and the drain 13 is commonly connected in the Y direction, this element alone will not work. It is not possible to have bit selectivity for convolution and erasure. In order to provide bit selectivity for writing and erasing, a selection transistor is provided separately in addition to the memory element, but '! l: The trap requires the provision of another control dart that capacitively couples to the floating dart. Adding the former option, Tosinnosta, would be a major disadvantage to the development of fruit plants, so conventionally, the method of adding a control gate for strawberries has been proposed as the most practical method. In this case, it has been considered to realize the floating gate and the two control I gates with a three-layer polysilicon structure.

However, the use of three-layer polysilicon complicates the cell structure and makes high-precision processing difficult in the resist process and polysilicon processing process due to thicker steps.

[Purpose of the invention]

The present invention is a non-volatile semiconductor memory device that has nonvolatile semiconductor memory elements having floating darts and control darts arranged in a matrix to provide bit selectivity in electrical rewriting, and has a simple fL structure that improves processability. An object of the present invention is to provide a semiconductor memory device.

[Summary of the invention]

A nonvolatile semiconductor memory device according to the present invention uses a structure in which a region for selective enrichment and erasing is provided separately from a channel region. That is, an impurity region is provided in the substrate that is continuous with the source or drain of the memory element,
A floating dart 'f' continuous from above the channel region is provided on this impurity region via an insulating film, and first and second control darts are provided so as to be capacitively coupled to this floating dirt. . As such a structure, 5- above 1. By selecting the potential relationship between the second control dart and the impurity region, charge can be exchanged between the impurity region and the floating dart above it.
The basic feature is that the memory cell array of the cell can be selectively rewritten.

In the basic structure as described above, the present invention is characterized in that the first and second control darts are formed by nodding an electrode film formed in one process so as to overlap the floating darts, and that the floating darts are formed into channels. A so-called offset dart structure is used to partially cover the area, and the remaining part is covered with the first. The present invention is characterized in that at least a portion of the second control dart is covered as a readout electrode.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a nonvolatile semiconductor memory device in which information can be electrically and selectively rewritten as a single element/cell configuration. Further, according to the present invention, the first and second
Since the control dart is formed by turning the same electrode film, the difference in level does not become large unlike when these are stacked, and therefore a highly reliable memory can be obtained with high processing precision. Furthermore, in the present invention, the initial state.

1. Both the included state and E type, and the floating goo 1 in the erased state.
- Toji 10, in which F is now D type, also uses the floating nine-gate as an offset gate structure and the first or second control dart as a readout electrode, so the unselected successive electrodes are set to zero potential. All selection operations can be performed without any inconvenience.

[Embodiments of the invention]

FIG. 2 shows the main structure of a memory device according to an embodiment of the present invention, in which (a) is a plan view, (b) and (C) are (-) A-A' and B-B, respectively. 'It's a cross section.

An n-type source 22. A drain 23 is provided, a floating dart 25 made of a first layer polysilicon film is provided on the channel region between these inner regions with a gate insulating film 24 interposed therebetween, and a second layer polysilicon film is further formed on top of the floating dart 25 with a dirt insulating film 26 interposed therebetween. First and second patterned silicon films
Control routs 27 and 28 are provided. As a region where information is inserted and erased, an n+ type layer 29 formed continuously with the source 22 is provided adjacent to the channel region, and a dirt insulating film thin enough to allow a tunnel current to flow is formed on this n+ type layer 29. 25 of the floating darts are extended through 30. As is clear from (a) and (b), the floating dirt 25 is located at the source 22. It has an offset (r-) structure with respect to the drain 23, that is, it does not cover the entire channel region, and the remaining portions are covered by the first and second control gates 27 and 28.

Note that this memory element is arranged in a matrix on the substrate, in which case the source 22 and the first control gate 2
7 are arranged continuously in the X direction, and the drain 23 and the second control gate 28 are commonly connected in the Y direction by, for example, an At wiring in the uppermost layer.

Scanning of the memory system is carried out by grounding the source 22 and drain 23 and applying a positive potential (for example, 20 V) i to the first and second control darts 27 and 28.
This is done by fully tunneling electrons from 9 to the floating goo 125.

Further, erasing is performed by setting the source 22 at a high potential (for example, 20 V), and grounding the first and second control darts 27 and 28 to cause a tunnel current to flow from the floating dart 25 to the n+ region 2.
This is done by emitting electrons at 9. In addition, the start-up is performed by applying a positive read voltage (for example, 5 V) to the first and second controls f-) 27 and 28 and detecting whether or not a child current flows.

When the memory elements are arranged in a matrix, the bit selectivity for writing and erasing is such that writing and erasing are performed only when the first and second control darts 27 and 28 are at the same potential or at the ground potential, respectively. This can be achieved by setting the connection valley cover of each part as shown in the figure.

Further, in this memory element, the floating gate 25 has an offset gate structure, thereby enabling selective reading. That is, in the erase operation, when the threshold value of F moves in the negative direction from the initial state and becomes a type D, the voltage is applied to the gate in the normal gate structure. The Naya electric current α1r also flows to the element in the non-selected state where the voltage is Ov. In the memory element of this embodiment, by setting the threshold value of the offset gate section to 1 V, for example, the unnecessary child current as described above is prevented from flowing, and successive selections can be made.

In this way, according to this embodiment, a nonvolatile memory that can be electrically and selectively rewritten with an L element/cell configuration is obtained. Also, 1st. Since the second control r-) is formed using the same polysilicon film, the surface unevenness is less stable than a three-layer polysilicon structure, so higher accuracy can be obtained in the Renost process and polysilicon film processing process, and the memory The reliability of the device is improved. Furthermore, by making the floating darts have an offset structure, the continuous selection operation can be performed reliably.

In addition, in the above embodiment, the source of floating dirt.

-1〇- Both sides of the drain are ososeso) It was built in 411, but the 3rd
As shown in the figure, a similar operation is possible even if only one side has an offset structure. In the above embodiments, an n-channel V case was explained, but the present invention can of course be applied to a p-channel as well.

[Brief explanation of the drawing]

FIGS. 1(a) to (C) are diagrams showing the structure of an example of a conventional nonvolatile memory, and FIGS. 2(a> to (C) are diagrams showing the structure of a nonvolatile memory according to an embodiment of the present invention. , FIG. 3 is a diagram showing the structure of a nonvolatile memory of another embodiment. 21...2m silicon substrate, 22...source, 23
...Drain, 24.26...X dirt insulating film, 25
...Floating dirt (first layer polysilicon film), 27...
・First 101''1i1141)/A-t (second layer polysilicon film), 28... second control dart (second layer polysilicon film), 29... n+ region 30... Dart insulation film. Applicant's agent Patent attorney Takehiko Suzue - 〇 = Figure 1 country - (N ('J field Figure 3-397-

Claims (1)

[Claims] In a nonvolatile semiconductor memory device in which memory elements having floating dirt and control dirt are integrated in a matrix on a semiconductor substrate, each memory element has a source and a drain formed on the semiconductor substrate at a distance from each other, and An impurity region of the same conductivity type that is formed continuously with the source or drain, floating dirt that is continuously formed on this impurity region and on the channel region between the source and drain with an insulating film interposed therebetween, and the floating dirt. first and second control gates provided so as to be capacitively coupled to the darts, the first and second control gates having an electrode film formed in one step on the floating r-). The floating cage is formed by slightly turning the floating gate so as to overlap with the first. A nonvolatile semiconductor memory device, characterized in that it is covered with at least one of the second control darts.