JPH0640589B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device, and more particularly to a programmable ROM capable of electrically rewriting data.

(Prior Art) Programmable RO that can electrically rewrite data
M, so-called E ² PROM (Electrically Erasable)
A memory cell used in an And Programmable ROM) has a cross sectional structure as shown in FIG.
This memory cell has a so-called three-layer polysilicon structure and utilizes the emission of electrons due to a tunnel current on the asperity or texture structure.

Reference numeral 80 is, for example, a P-type semiconductor substrate, and 81 is an N-type diffusion layer serving as a source region. A first electrode 82 made of a first-layer polycrystalline silicon layer is formed on the diffusion layer 81 via an insulating film.
Is provided. Further, a second electrode 83 made of a second-layer polycrystalline silicon layer is provided on the first electrode 82 via an insulating film. The second electrode 83 is also provided on the diffusion layer 81 via an insulating film. The second electrode 83 is in an electrically floating state.
Further, a third electrode 84 made of a third-layer polycrystalline silicon layer is provided on the second electrode 83 via an insulating film. The upper surfaces of the first electrode 82 and the second electrode 83 have an asperity or texture structure.
Here, the second electrode 83 is used as a floating gate electrode and the third electrode 84 is used as a control electrode.

Now, the third electrode 84 is at a high potential Vpp, for example + 20V,
When the first electrode 82 is set to the ground potential GND (0V) and the diffusion layer 81 is set to the ground potential GND, respectively, the third electrode 84 and the second electrode 83, the second electrode 83 and the first electrode
The potential of the second electrode 83 in the floating state is set to a relatively low potential due to the capacitive coupling between the second electrode 83 and the diffusion layer 81. As a result, if electrons are injected into the second electrode 83 in advance, the second electrode 83 to the third electrode
Electrons are emitted to the electrode 84 to erase it.

On the other hand, when the third electrode 84 is set to the high potential Vpp, the first electrode 82 is set to the ground potential GND, and the diffusion layer 81 is set to the high potential Vpp, the potential of the second electrode 83 is set to a relatively high potential. It As a result, electrons are injected from the first electrode 82 to the second electrode 83, and writing is performed.

Here, since the second electrode 83 is in an electrically floating state, the injected electrons continue to be stored as they are unless erase is performed. That is, the memory cell having the structure shown in FIG. 5 has a non-volatile characteristic.

FIG. 6 is a schematic circuit diagram when a memory cell array is actually formed by using the memory cells having the above structure. In the figure, 90 are memory cells, and these memory cell arrays are shown in a matrix of 3 rows × 3 columns for convenience of explanation. Reference numeral 91 is a common third electrode wiring of each of the three memory cells arranged in the same row, 92 is a common source wiring of each of the three memory cells arranged in the same row, and 93 Is a common first electrode wiring of each of the three memory cells arranged in the same column.

Here, the biggest problem of the memory cell array using the memory cell of FIG. 5 is that some memory cells other than the selected cell are brought into a semi-selected state. For example, in order to select another memory cell 90A, only the first electrode wiring 93B is set to "L", the remaining first electrode wirings 93A and 93C are both set to "H", and only the third electrode wiring 91B is set. The remaining third electrode wirings 91A and 91C are both set to "L" to "L". At this time, in the memory cell 90B, since the first electrode wiring 93 and the third electrode wiring 91 are both set to "H", electrons are slightly emitted from the second electrode depending on the potential of the source wiring 92. That is, this memory cell 90B is brought into a half-selected state. Also, the memory cell 90
Regarding C, since the first electrode wiring 93 and the third electrode wiring 91 are both set to “L”, electrons are slightly injected into the second electrode depending on the potential of the source wiring 92. That is, this memory cell 90C is brought into a half-selected state.

Conventionally, since a memory cell in such a half-selected state is generated, there is a problem that data destruction in a non-selected cell occurs due to repeated erasing and writing cycles due to long-term use, which lowers reliability. is there.

(Problems to be Solved by the Invention) As described above, in the conventional case, when a memory cell array is configured, some cells are brought into a semi-selected state, which is a factor that reduces reliability as a memory device.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a non-volatile semiconductor memory device capable of improving reliability by eliminating cells in a semi-selected state. To do.

[Structure of the Invention] (Means for Solving Problems) A nonvolatile semiconductor memory device of the present invention is a semiconductor substrate of a first conductivity type, and a first conductivity type first substrate formed in the substrate.
A diffusion layer, a second diffusion layer of the second conductivity type formed at a predetermined distance from the first diffusion layer and supplied with a programming potential, and formed in the substrate and supplied with a reference potential. A third diffusion layer of the second conductivity type, a fourth diffusion layer of the second conductivity type formed at a predetermined distance from the third diffusion layer, and a fourth diffusion layer at a predetermined distance from the fourth diffusion layer. And a fifth diffusion layer of the second conductivity type, to which a reading potential is supplied, and an insulating film so as to overlap the first diffusion layer, and a part of the third diffusion layer and the fourth diffusion layer. The third diffusion layer is provided so as to overlap with the first electrode that is extended to be located between the first electrode and is set in an electrically floating state, and the first electrode and the first diffusion layer, respectively. A second electrode connected to the first electrode, and a third electrode provided via an insulating film so as to overlap the first electrode, Note that the fourth electrode is continuously provided on the channel region between the first and second diffusion layers and on the channel region between the fourth and fifth diffusion layers with an insulating film interposed therebetween. .

(Operation) In the nonvolatile semiconductor memory device of the present invention, the first diffusion layer can be separated from the programming potential in accordance with the signal of the fourth electrode.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a pattern plan view showing the structure of a memory cell used in the nonvolatile semiconductor memory device of the present invention.
The drawing is a sectional view taken along the line AA '.

In the figure, 10 is a P-type substrate, and this substrate 10 has N
Diffusion layers 11, 12, 13, 14 and 15 of the mold are separately formed. Here, the programming potential is supplied to the diffusion layer 12, the reference potential, that is, the ground potential is constantly supplied to the diffusion layer 13, and the diffusion layer 15 is used for reading. The electric potential is supplied.

A second electrode 17 formed of a first-layer polycrystalline silicon layer is provided on the diffusion layer 11 via an insulating film 16. The second electrode 17 is connected via the direct contact portion 18 to the diffusion layer 13 which is always set to the ground potential. Further, a first polycrystalline silicon layer of a second layer is formed on the diffusion layer 11 with the insulating film 16 interposed therebetween.
An electrode 19 is provided. The first electrode 19 covers the second electrode 17 through the insulating film 20, and further the diffusion layer is formed.
It extends so as to cover the insulating film 16 provided on the channel region set on the substrate surface between 13 and 14. The first electrode 19 is set in an electrically floating state.

A third electrode 22 composed of a third-layer polycrystalline silicon layer is provided on the first electrode 19 via an insulating film 21.

Also, an insulating film (not shown) provided on the channel region set on the substrate surface between the diffusion layers 11 and 12 and a channel region set on the substrate surface between the diffusion layers 14 and 15 A fourth electrode composed of a third-layer polycrystalline silicon layer so as to continuously cover an insulating film (not shown) provided above.
23 are provided. In addition, the first electrode 19 and the second electrode 17
The top surface of each is either asperity or textured.

FIG. 3 is an equivalent circuit diagram of the memory cell having the above configuration. Here, 31 is an erasing / writing element, 32 is this erasing / writing element.
A selection transistor for selecting the writing element 31, a data reading transistor 33 to which the storage data of the erasing / writing element 31 is given, a selection transistor 34 for selecting the data reading transistor 33, a control electrode 35,
36 is a selection electrode. The selecting transistor 32 and the erasing / writing element 31 are connected in series between the programming potential E / W and the ground potential GND, and the selecting transistor 34 and the data reading transistor 33 are connected to the reading potential R. It is connected in series with the ground potential GND.

The erasing / writing element 31 has the diffusion layer 11 as a drain, the first electrode 19 as a floating gate electrode, and the third electrode 22 as a control electrode. Here, the capacitance connected between the floating gate electrode and the drain of this element 31 is in the region where the diffusion layer 11 and the first electrode 19 overlap each other. The selection transistor 32 is configured with the diffusion layer 11 as a source, the diffusion layer 12 as a drain, and the fourth electrode 23 as a gate electrode. The data reading transistor 33 is configured as a floating gate type transistor in which the diffusion layer 13 is the source, the diffusion layer 14 is the drain, the first electrode 19 is the floating gate electrode, and the third electrode 22 is the control gate electrode. The selection transistor 34 includes the diffusion layer 14 as a source, the diffusion layer 15 as a drain, and the fourth electrode 23 as a gate electrode.

When selecting such a memory cell for programming, a high potential Vpp of about +20 V is supplied to both the selection electrode 36 and the control electrode 35, and a programming potential E / W is supplied to the drain of the selection transistor 32. It When the selection electrode 36 is set to the high potential Vpp, the selection transistor 32 is turned on, and the programming potential E /
W is applied to the drain of the erase / write element 31.

Here, when erasing data in the selected memory cell, the ground potential is supplied as the programming potential E / W. Since the second power source 17 (shown in FIG. 1) is always set to the ground potential, in the erasing / writing element 31, the third electrode 22 and the first electrode 19, the second electrode 17 and the first electrode 1 are used.
9. The capacitive coupling between the second electrode 19 and the diffusion layer 11 makes the potential of the second electrode 19 in a floating state relatively low. Accordingly, if electrons are injected into the second electrode 19 in advance, the second electrode 19 to the third electrode
Electrons are emitted to the electrode 22 and erased.

When writing data, program potential E
The high potential Vpp is supplied as / W. At this time, since a potential close to Vpp is applied to the drain of the erasing / writing element 31, the potential of the second electrode 19 is set to a relatively high potential. As a result, electrons are injected from the first electrode 17 to the second electrode 19, and writing is performed.

Here, since the second electrode 19 is in an electrically floating state, electrons that have been once injected continue to be stored in the second electrode 19 as they are unless erase is performed. That is, this memory cell has a non-volatile characteristic.

On the other hand, at the time of the above programming, in the memory cell which is not selected, both the selection electrode 36 and the control electrode 35 are set to the ground potential. Therefore, the selection transistor 32 is turned off, and the programming potential E / W is set to the erase / write element.
It is not applied to the drain of 31. Here, since the second electrode 17 set to the ground potential partially overlaps the diffusion layer 11 via the insulating film 16, the drain of the erasing / writing element 31 is set to almost the ground potential. Therefore, in the erase / write element 31 of the unselected memory cell, the second
The electrode 19, the third electrode 22, and the diffusion layer 11 are all set to the ground potential, and the emission of electrons from the first electrode 19 and the first electrode
No electrons are injected into 19.

In the data read operation in the memory cell, both the selection electrode 36 and the control electrode 35 are set to the potential of + 5V, and the drain R of the selection transistor 34 is supplied with the read potential R of + 5V. When the selection electrode 36 is set to the potential of + 5V, the selection transistor 34 is turned on, and the read potential R of + 5V is applied to the drain of the data read transistor 33. Here, the floating gate electrode of the transistor 33 is shared with the erasing / writing element 21. Therefore, if electrons are injected into the floating gate electrode (second electrode 19) in advance, the threshold voltage is 5
The threshold voltage is set to a high value of V or higher, and the threshold voltage is set to a low value of 5 V or lower if electrons are emitted from the floating gate electrode. Then, when a potential of +5 V is applied to the control electrode 35, the transistor 33 is turned on or off depending on the electron injection state of the floating gate electrode of the transistor 33. When the transistor 33 is on, the + 5V read potential R applied to the drain is discharged to the ground potential, and when the transistor 33 is off, the + 5V read potential R applied to the drain is held as it is. .

FIG. 4 shows a configuration of an application circuit of the present invention. This circuit is a case where a memory having a structure of 8 bits for one word is constructed by using the memory cells having the structure shown in FIG.

In the figure, the memory cells 40 having the structure shown in FIG. 3 are arranged in a matrix. In these memory cells 40,
The selection electrodes 36 of the memory cells 40 arranged in the same row are commonly connected to one of the m word lines to which the output of the row decoder is supplied. Further, the memory cells 40 arranged in the same row are divided into n blocks with 8 blocks each corresponding to the bit number of 1 word as 1 block. The number of n corresponds to the output of the column decoder. The control electrode 35 of the eight memory cells 40 in each block is a depletion type MOS transistor in which the signal of the word line of the corresponding row is supplied to the gate electrode.
The column selection line of the corresponding column is connected to the supply point of the potential Vpp / Vcc via the depletion type MOS transistor 42 in which signals of 1C to nC are supplied to the gate electrode in series.

Further, the drains of the respective selection transistors 32 in the eight memory cells 40 in one block have eight enhancement types in which the signal of the column selection line C of the corresponding column is supplied to the gate electrodes in parallel. Is connected to each erase / write potential E / W via the MOS transistor 43. Further, the drains of the respective selection transistors 34 in the eight memory cells 40 in one block have eight enhancement types in which the signal of the column selection line C of the corresponding column is supplied to the gate electrodes in parallel. Is connected to each read potential R via the MOS transistor 44.

In the program operation of the memory having such a configuration, one of the outputs of the column decoder and the row decoder is set to the high potential Vpp. As a result, the control electrodes 35 in the eight memory cells 40 in the block corresponding to the selected column and row are connected through the transistors 42 and 41 in series.
Is supplied with a high potential Vpp. Further, the erasing / writing potentials E / are connected to the drains of the erasing / writing elements 31 in the eight memory cells 40 via the transistors 43 and the internal selection transistors 32 in series.
W is supplied. In the other memory cells in the non-selected state, only the threshold voltage of the depletion type transistor 41, which is about 2 V at most, is applied to the control electrode 35, and the transistor 43 for column selection is turned off. No potential is applied to the drain of the element 31.

As described above, the memory cell of the above-described embodiment does not have the conventional half-selected state. Therefore, even if the erase and write cycles are repeated due to long-term use,
Data destruction does not occur in non-selected cells. As a result, the reliability can be significantly improved.

[Effect of the Invention] As described above, according to the present invention, it is possible to provide a non-volatile semiconductor memory device that can eliminate cells in a half-selected state and can improve reliability. it can.

[Brief description of drawings]

FIG. 1 is a pattern plan view showing the structure of a memory cell according to an embodiment of the present invention, FIG. 2 is a sectional view thereof, FIG. 3 is an equivalent circuit diagram of the memory cell of FIG. 1, and FIG. Circuit diagram of application circuit of example, FIG. 5 is a sectional view of a conventional memory cell,
FIG. 6 is a schematic circuit diagram of a memory cell array using the memory cell of FIG. 10 ... Substrate, 11, 12, 13, 14, 15 ... Diffusion layer, 16, 20,
21 ... Insulating film, 17 ... Second electrode, 18 ... Direct contact part, 19 ... First electrode, 22 ... Third electrode, 23 ...
Fourth electrode, 31 ... Erase / write element, 32 ... Selection transistor, 33 ... Data reading transistor, 34 ...
… Transistor for selection, 35 …… Control electrode, 36 …… Selection electrode, 41,42 …… Depletion type MOS transistor, 43,44 …… Transistor for column selection.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koichi Kanzaki 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki City, Kanagawa Prefecture, Toshiba Research Institute Co., Ltd. (56) Reference JP-A-61-265869 (JP, A)

Claims (2)

[Claims] 1. A first conductivity type semiconductor substrate, a second conductivity type first diffusion layer formed in the substrate, and a programming potential formed at a predetermined distance from the first diffusion layer. A second diffusion layer of a second conductivity type to which is supplied, a third diffusion layer of a second conductivity type that is formed in the substrate and is supplied with a reference potential, and a predetermined distance from the third diffusion layer. A fourth diffusion layer of the second conductivity type formed by the above, a fifth diffusion layer of the second conductivity type which is formed at a predetermined distance from the fourth diffusion layer and to which a read potential is supplied, A first electrode which is provided so as to overlap the first diffusion layer with an insulating film interposed between them and which is extended so that a part thereof is located between the third and fourth diffusion layers and which is set in an electrically floating state; , Provided via an insulating film so as to overlap with each of the first electrode and the first diffusion layer, and connected to the third diffusion layer. The second electrode formed on the channel region between the first and second diffusion layers and the third electrode provided via the insulating film so as to overlap the first electrode, and the fourth and fifth diffusions. A non-volatile semiconductor memory device, comprising: a fourth electrode continuously provided on a channel region between layers via an insulating film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein each of the first, second, third and fourth electrodes is composed of a polycrystalline silicon layer.