JP2807382B2 - Nonvolatile storage device and method for writing information therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEPROM (Ele
ctrically Erasable Programmable Read OnMemory)
The present invention relates to a nonvolatile storage device including a nonvolatile storage element that stores information by injecting or extracting charge.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile memory element (hereinafter, referred to as a nonvolatile memory element) which stores data by injecting or extracting electric charge.
Various types of non-volatile memory devices (hereinafter, referred to as “non-volatile memories”) having “memory transistors” have been proposed. FIG. 8 shows an example of the nonvolatile memory. FIG. 8 is a perspective view showing the structure of a conventional nonvolatile memory.
This nonvolatile memory MD is a flash EEPROM. As shown in FIG. 8, a plurality of flash memory transistors MTr are formed on a single P-type silicon substrate 1 in a matrix in the row direction X and the column direction Y. Have been.

In the nonvolatile memory MD, a plurality of LOCOS (local oxidation of silicon) films 2 are formed in the surface layer of the P-type silicon substrate 1 along the memory transistors MTr arranged in the column direction Y. When,
Immediately below each LOCOS film 2, they are formed at predetermined intervals in the column direction Y, and the source and drain regions are shared by the memory transistors MTr adjacent in the row direction X to form source / drain wiring. Floating gate 5 formed to be surrounded by an insulating film on N ⁺ type buried impurity diffusion layer 3 and channel region 4 formed to be sandwiched between buried impurity diffusion layers 3.
And a control gate 6 formed along the row direction X above each floating gate 5 and shared by the memory transistors MTr arranged in the row direction X and serving as a gate wiring.

That is, the non-volatile memory MD is a so-called virtual ground array which does not make contact with the impurity diffusion layer 3 and the control gate 6 on the silicon substrate 1, thereby increasing the height of the memory transistor MTr. We are trying to implement density mounting. FIG. 9 is an explanatory diagram schematically showing the operation of the memory transistor at the time of writing data. In the memory transistor MTr, data is written from the drain region 3b side of the buried impurity diffusion layer 3, as shown in FIG. That is, writing is performed by the control gate 6-
A high electric field is applied between the drain region 3b and the source region 3a
-Saturated channel current is passed between the drain regions 3b. Pinch off region (pinct off) near the drain region 3b
region), the electrons accelerated by the high electric field cause ionization (impact ionization), so-called channel hot electrons are generated, and the channel hot electrons cause the tunnel oxide film 7 on the channel region 4 to FN (Fow).
(ler-Nordheim) Tunneled and injected into the floating gate 5. The electrons injected into the floating gate 5 turn ONO (oxide
-Nitride Oxide) The film 8 is confined in the floating gate 5 for a long time.

[0005]

With the recent development of the semiconductor industry, there has been a demand for higher speed devices. Therefore, in the nonvolatile memory shown in FIG. 8, there is a need in design to reduce the drain voltage of the memory transistor as much as possible for the following two reasons in order to speed up data writing.

[0006] The drain withstand voltage when the memory transistor is turned on is set to a low voltage to reduce the size of the drain region. Reduces current consumption when writing data. Therefore, in order to reduce the drain voltage to about 4 V or 5 V, it has been considered to increase the gate voltage and raise channel hot electrons to the floating gate to improve the writing speed.

However, when writing data from the drain side, if the gate voltage is increased while keeping the drain voltage constant, the injection current will increase at first, but the generation of channel hot electrons is optimal at a certain gate voltage. Therefore, even if the drain voltage is fixed and the gate voltage is increased, the electric field along the channel direction near the drain is weakened. Therefore, the generation of hot electrons is reduced, and the efficiency of injecting electrons into the floating gate is not so high.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a non-volatile memory device capable of writing data at high speed by increasing the charge injection efficiency.

[0009]

According to the present invention, there is provided a non-volatile memory device for injecting and extracting electric charges onto and from a single semiconductor substrate having a predetermined first conductivity type. A nonvolatile memory device in which a plurality of nonvolatile memory elements for storing information are arranged in a matrix in a row direction and a column direction, and are arranged in a column direction on a surface layer of the semiconductor substrate. And a plurality of LOCOS insulating films formed thick along the non-volatile memory elements, and each non-volatile memory formed immediately below each LOCOS insulating film at predetermined intervals in the column direction and adjacent in the row direction. A buried impurity diffusion layer of a second conductivity type opposite to the first conductivity type, wherein the buried impurity diffusion layer is a bit line by sharing a source region and a drain region between the devices; A gate insulating film formed on a predetermined region on the source region side of a channel region formed so as to be sandwiched between the embedded impurity diffusion layers, and a column formed on each of the gate insulating films in a column direction, The select gate line is shared by each of the nonvolatile memory elements arranged in the direction, and is formed on each channel region except for the predetermined region on the source region side and the select gate line, which is generated in each channel region. Pass a charge having high energy, and a tunnel insulating film having a thickness smaller than the gate insulating film, formed on each of the tunnel insulating films, accumulates the charge that has passed through the tunnel insulating film, A plurality of charge storage layers whose end portions on the source region side cover a partial region of each of the select gates with an insulating film interposed therebetween; In, is formed along the row direction, it is intended to include a gate that is a word line shared by the non-volatile storage elements with each other to be arranged in the row direction.

In the above-described method for writing information in a nonvolatile memory device, the method is such that the channel of the nonvolatile memory element is turned on with respect to a select gate line serving as a select gate of the nonvolatile memory element for writing information. A voltage is applied, and a high voltage is applied to a word line serving as a gate. At the time of writing information, in the selected nonvolatile memory element, a surface potential gradient is generated between the select gate and the charge storage layer, and concentrated under the tunnel insulating film between the select gate and the charge storage layer. An electric field is applied. Here, charge having high energy is generated, and this charge is injected from the source region side of the charge storage layer through FN tunneling through the tunnel insulating film.

As described above, by injecting charges from the source region side, regardless of the current between the source region and the drain region, the injection current between the charge storage layer and the select gate increases as the gate voltage increases. To keep growing,
Information can be written without decreasing the speed.

[0012]

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view of a nonvolatile memory according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II of FIG. The structure of the nonvolatile memory MD1 according to the present embodiment will be described with reference to FIGS. 1 and 2
Indicates a state where the passivation film has been peeled off.

The non-volatile memory MD1 of this embodiment is a flash EEPROM, and as shown in FIG. 1, a plurality of memories for storing data by injecting or extracting electrons into or from a single P-type silicon substrate 11. Flash memory transistors MTr11, MTr12, MTr13, MTr
14, MTr15, MTr16 are arranged in a matrix along the row direction X and the column direction Y.

As shown in FIGS. 1 and 2, the memory transistors MTr11, MTr14 and MTr12, MTr arranged in the column direction Y are provided on the surface layer of the P-type silicon substrate 11.
LOC along r15 and MTr13, MTr16
OS films 121, 122, 123, and 124 are formed. In the figure, immediately below the left end LOCOS film 121, the memory transistors MTr11 and MT arranged in the column direction Y are arranged.
r14 source region 13a, that is, bit line BL
The N ⁺ type buried impurity diffusion layer 131 which is 1 is formed along the column direction Y. Immediately below the right end LOCOS film 124, an N ⁺ -type buried impurity diffusion layer 134 that becomes the drain region 13b of the memory transistors MTr13 and MTr16 arranged in the column direction Y, that is, the bit line BL4 is formed along the column direction Y. Have been. Further, immediately below the LOCOS film 122, the drain regions 13b of the memory transistors MTr11 and MTr14 and the memory transistors MTr12,
An N ⁺ -type buried impurity diffusion layer 132 serving as the source region 13a of the MTr 15, that is, the bit line BL2 is formed along the column direction Y at a predetermined interval from the buried impurity diffusion layer 131. Similarly, the LOCOS film 12
Immediately below the N ² , an N ⁺ -type buried impurity diffusion layer 133 that becomes the drain region 13b of the memory transistors MTr12 and MTr15 and the source region 13a of the memory transistors MTr13 and MTr16, that is, the bit line BL3, is buried. Impurity diffusion layer 1
32 and the buried impurity diffusion layer 134 at predetermined intervals along the column direction Y. That is, the buried impurity diffusion layer 132 serving as the bit line BL2
Is the memory transistor MTr1 adjacent in the row direction X
1, MTr12 and memory transistor MTr14,
The buried impurity diffusion layer 133 shared by the MTr 15 and serving as the bit line BL3 is adjacent to the row direction X.
The memory transistors MTr12 and MTr13 and the memory transistors MTr15 and MTr16 are shared.

Each of the buried impurity diffusion layers 131, 132,
Gate oxide films 15 are respectively formed on predetermined regions on the source region 13a side of the channel regions 14 which are respectively sandwiched between the 133 and 134. Memory transistors MTr11, MT arranged in column direction Y
The select gate 161 serving as the select gate line SGL1 is formed on the gate oxide film 15 in the r14 formation region.
Are formed along the column direction Y. Similarly, each of the memory transistors MTr12, MTr arranged in the column direction Y
The select gate 16 serving as the select gate line SGL2 is formed on the gate oxide film 15 in the Tr15 formation region.
2 are formed along the column direction Y. Further, each of the memory transistors MTr13, MT arranged in the column direction Y
The select gate 163 serving as the select gate line SGL3 is formed on the gate oxide film 15 in the r16 formation region.
Are formed along the column direction Y. That is, the select gate 162 serving as the select gate line SGL1 is connected to the memory transistors MT arranged in the column direction Y.
r11, shared by MTr14, select gate line S
The select gate 162 of GL2 is in the column direction Y
Memory transistors MTr12, MTr15 arranged in
And the select gate 163 serving as the select gate line SGL3 is shared by the memory transistors MTr13 and MTr16 arranged in the column direction Y.

Each of the buried impurity diffusion layers 13
A tunnel oxide film 17 capable of tunneling channel hot electrons generated in each channel region 14 is formed on each of the channel regions 14 excluding a predetermined region on the side of the source region 13a of 1, 132, 133, and 134. I have. Floating gates 181, 182, 183, and 18 that accumulate electrons tunneling through each tunnel oxide film 17 are formed on each tunnel oxide film 17.
4, 185, 186 are formed.

Each floating gate 181, 182,
183, floating gates 181, 18
An ONO film 19 for keeping the electrons accumulated in 2,183 confined for a long time is formed.
Memory transistors MTr11, M arranged in row direction X
On the ONO film 19 in the Tr12 and MTr13 formation regions,
Control gate 2 serving as word line WL1
01 is formed along the row direction X. Further, the memory transistors MTr14 and MTr1 arranged in the row direction X
5, a control gate 202 serving as a word line WL2 is formed along the row direction X on the ONO film 19 in the MTr16 formation region. That is, the control gate 201 serving as the word line WL1 is
Memory transistors MTr11, M arranged in row direction X
Tr12 and MTr13 share the word line W
The control gate 202 at L2 is connected to the memory transistors MTr14 and MTr1 arranged in the row direction X.
5, shared by MTr16.

In the following description, the memory transistors MTr11, MTr12, MTr13, MTr1
4, MTr15 and MTr16 are collectively referred to as “memory transistor MTr1”. LOCOS film 1
21, 122, 123, and 124 are collectively referred to as “LO
COS film 12 "and buried impurity diffusion layers 131 and 13
2, 133 and 134 are collectively referred to as "buried impurity diffusion layer 13" and select gates 161, 162, 16
3 are collectively referred to as "select gate 16" and floating gates 181, 182, 183, 184, 18
5, 186 are collectively referred to as “floating gate 1
8 "and the control gates 201 and 202 are collectively referred to as" control gate 20 ".

The P-type silicon substrate 11 has a specific resistance of 5-2.
As low as 0 Ωcm is used. LOCO
The S film 12 is made of SiO ₂ and has a thickness of about 10,000 約.
It is provided as thick as possible. The gate oxide film 15 is made of Si
It is made of O ₂ and has a thin film thickness of about 150 °.

The select gate 16 is made of, for example, a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce the resistance. The end of the select gate 16 on the source region 13 a side extends to the upper part of the LOCOS film 12. Have been banished.
The tunnel oxide film 17 is made of SiO ₂ and has a very small thickness of about 100 ° so as to tunnel electrons. Then, the tunnel oxide film 17
Of the select gate 16 extends to a position immediately below the end of the select gate 16 on the drain region 13b side.

The floating gate 18 is made of a conductive material such as polysilicon whose resistance is reduced by doping phosphorus at a high concentration, and is provided at a predetermined distance from the select gate 16. The end of the floating gate 18 on the source region 13a side is connected to the select gate 16.
, A predetermined region on the side of the drain region 13 b is covered, and an end on the side of the drain region 13 b is connected to the LOCOS film 12.

The ONO film 19 has a structure in which a nitride film such as Si ₃ N ₄ is sandwiched from above and below by an oxide film such as SiO ₂ . The bottom oxide film has a thickness of about 100 °, the nitride film has a thickness of about 150 °, and the top oxide film has a thickness of about 50 °. The control gate 20 is made of, for example, a conductive material such as polysilicon whose resistance is reduced by doping phosphorus at a high concentration.

Further, between the select gate 16 and the control gate 20 and between the select gate 16 and the floating gate 18, B in which PSG (phospho-silicate glass) which is P-doped SiO ₂ is mixed.
An interlayer insulating film 21 made of an insulating material such as PSG (bron-phospho-silicate glass) is filled. Therefore, the space between the select gate 16 and the control gate 20 and the space between the select gate 16 and the floating gate 18 are insulated. In addition, the floating gate 18
LOCOS film 12, tunnel oxide film 17, O
It is surrounded by the NO film 19 and the interlayer insulating film 21 and has no external connection.

Further, although not shown, the memory transistor MTr1
A passivation film made of, for example, an insulating material such as PSG is laminated in order to protect the surface of the device and prevent intrusion of contaminants from the outside. As described above, the nonvolatile memory MD1 is a so-called virtual ground array that does not make contact with the buried impurity diffusion layer 13 and the control gate 20 on the silicon substrate 11, thereby achieving high-density mounting of the memory transistors MTr1. I have.

FIG. 3 is an equivalent circuit diagram of the nonvolatile memory. The electrical configuration of the nonvolatile memory MD1 will be described with reference to FIG. The nonvolatile memory MD1 is
As shown in FIG. 3, six memory cells including a memory cell MC11 indicated by reference numerals are arranged, and each memory cell has a one-cell / one-transistor structure including one memory transistor MTr1.

The word line WL1 is connected to the control gates of the memory transistors MTr11, MTr12, MTr13 arranged in the row direction X, and the memory transistors MTr14, MTr arranged in the row direction X.
The word line WL2 is connected to the control gates of the reference numeral 15 and MTr16. The select gate line SGL1 is connected to the select gates of the memory transistors MTr11 and MTr13 arranged in the column direction Y, and the memory transistors MTr12 and MTr arranged in the column direction Y.
Select gate line SG for select gate of Tr15
L2 is connected, and a select gate line SGL3 is connected to select gates of the memory transistors MTr13 and MTr16 arranged in the column direction Y.

Further, the bit line BL1 is connected to the sources of the memory transistors MTr11 and MTr14 arranged in the column direction Y, and the bit line BL4 is connected to the drains of the memory transistors MTr13 and MTr16 arranged in the column direction Y. The sources and drains of the memory transistors MTr11, MTr12 and MTr14, MTr15 adjacent in the row direction X are connected in series, and the bit line BL2 is connected to the connection midpoint. Similarly, memory transistors MTr12, MTr13 and MTr15, which are adjacent in the row direction X,
The source and the drain of the MTr 16 are connected in series, and the bit line BL3 is connected to the connection midpoint.

Here, the operation of writing, erasing, and reading data in the nonvolatile memory MD1 will be described mainly with reference to FIG. 3 and Table 1. In Table 1, it is assumed that the memory cell MC11 shown in FIG. 3 is selected.

[0029]

[Table 1]

<Write> The word line WL2 and the select gates SGL2 and SGL3 are set to the ground potential 0V, and 5V is applied to the bit lines BL2, BL3 and BL4 to select the memory cell MC11 to which data is to be written. To this end, the bit line BL1 is set to the ground potential 0V, 1.5V is applied to the select gate line SGL1 as soon as the channel of the memory transistor MTr11 is turned on, and a high voltage 14V is applied to the word line WL1.

Then, as shown in FIG. 4, the memory transistor MTr1 in the selected memory cell MC11
In 1, the surface potential gradient is generated between the select gate 161 and the floating gate 181, and an electric field is concentrated under the tunnel oxide film 17 between the select gate 161 and the floating gate 181. Here, the electrons are accelerated to generate channel hot electrons. The hot electrons are injected through the FN tunnel from the source region 13a side of the floating gate 181 to be in a state of writing data "1".

On the other hand, in the memory transistor in the non-selected memory cell, no surface potential gradient is generated between the select gate and the floating gate, and no injection current is generated. Therefore, channel hot electrons are not injected into the floating gate. That is, no data is written. A gate voltage required for conducting between the source and the drain of the memory transistor changes between a state where electrons are stored in the floating gate and a state where electrons are not stored in the floating gate. That is, the threshold voltage V _TH for conducting between the source and the drain of the memory transistor is a high threshold V 1 (for example, 6 V) when electrons are injected into the floating gate.
And takes a low threshold value V2 (for example, 1 V) in a state where electrons are not injected. Thus, by setting the threshold voltage V _TH to two types, binary data of “1” or “0” can be stored in the memory transistor. <Erase> The word line WL2, the select gates SGL1, SGL2, SGL3 and the bit lines BL3, BL4 are set to the ground potential 0V, and the bit line BL1 is opened to select the memory cell MC11 from which data is to be erased. ) State and the bit line BL2
, And -6 V is applied to the word line WL1.

Then, as shown in FIG. 5, the memory transistor MTr1 in the selected memory cell MC11
1, an FN tunnel current is generated between the floating gate 181 and the drain region 13b of the buried impurity diffusion layer 132, and electrons accumulated in the floating gate 181 flow through the FN tunnel to the drain region 13b and are removed. As a result, the data is erased, that is, the data "0" is written.

On the other hand, in the memory transistor in the non-selected memory cell, no FN tunnel current occurs between the floating gate and the drain region, and electrons accumulated in the floating gate do not flow to the drain region. Is not erased. <Read (READ)> Word line WL2, select gates SGL2, SGL3, bit line BL
1, BL3 and BL4 are set to the ground potential 0 V, and the select gate SG is selected to select the memory cell 1 from which data is to be read.
5V is applied to L1, 2V is applied to bit line BL2, and 3V is applied to word line WL1.

Then, as shown in FIGS. 6A and 6B, in the memory transistor MTr11 in the selected memory cell MC11, since 5 V is applied to the select gate 161, the P-type transistor immediately below the select gate 161 is applied. Electrons having a concentration equal to the hole concentration of the silicon substrate 11 are induced on the surface of the silicon substrate 11, and an inversion layer (inversion layer) IL is generated.

At this time, as shown in FIG. 6A, if electrons are accumulated in the floating gate 181, the positive charge of the control gate 201 is canceled by the electrons injected into the floating gate 181. The influence of this positive charge does not reach the surface of the silicon substrate 11 immediately below the floating gate 181. Accordingly, no channel is formed in the memory transistor MTr11, and no current flows from the drain region 13b of the buried impurity diffusion layer 132 to the source region 13a of the buried impurity diffusion layer 131. On the other hand, as shown in FIG. 6B, if electrons are not accumulated in the floating gate 181, the control gate 201
Influences the surface of the silicon substrate 11 immediately below the floating gate 181. Therefore, a channel is formed in memory transistor MTr11, and a current flows from drain region 13b of buried impurity diffusion layer 132 to source region 13a of buried impurity diffusion layer 131. If this state is sensed by a decoder and a sense amplifier (not shown), the data stored in the memory transistor MTr11 is read.

Here, the sense voltage is an intermediate voltage between the two types of V1 and V2 of the threshold voltage _VTH .
Therefore, when this sense voltage is applied, whether or not electrons are accumulated in the floating gate
The conduction / non-conduction of the memory transistor is determined. The memory transistor MTr includes a buried impurity diffusion layer 1.
A gate oxide film 15 formed on a predetermined region on the source region 13a side of the channel region 14 generated so as to be sandwiched by the gate region 3; a select gate 16 formed on the gate oxide film 15; And a tunnel oxide film 17 having a thickness smaller than that of the gate oxide film 15 and formed on the tunnel oxide film 17 except for the predetermined region, and having an end portion on the source region 13a side facing the interlayer insulating film. 21, the floating gate 18 covering a part of the select gate 16 with the floating gate 18 interposed therebetween.
6, a gradient of the surface potential is generated, and channel hot electrons are generated efficiently, and the hot electrons can be injected from the source region 13a side of the floating gate 18.

As described above, by injecting hot electrons from the source region 13a side, the source region 13
Irrespective of the current between the a-drain region 13b, the injection current between the floating gate 18 and the select gate 16 continues to increase as the voltage applied to the control gate 20 increases, so that data writing can be performed without reducing the speed. It can be carried out.

As described above, since the generation of hot electrons occurs independently of the current between the source region 13a and the drain region 13b, the impurity concentration on the side of the drain region 13b is optimized considering only data erasure. Can be
Also, on the gate oxide film 15, the select gate 1
6 with the memory transistors MTr adjacent in the column direction Y.
11, MTr14 and MTr12, MTr15, and MTr13, MTr16, and are formed along the column direction Y so as to be select gate lines SGL1, SGL2, and SGL3.
Does not need to provide a contact by providing a contact hole on the silicon substrate 11, and it is possible to avoid increasing the resistance of the select gate line.

Further, the buried impurity diffusion layer 13 serving as the source region 13a and the drain region 13b is
Since it is formed immediately below the OS film 12, the select gate 1
Even if 6 is displaced, it does not affect the channel length. This is because, as shown in FIG.
After a buried impurity diffusion layer 13 is formed immediately below the COS film 12 and a channel length is defined between the LOCOS films 12,
A silicon oxide film 30 and a polysilicon 31 are sequentially laminated,
Thereafter, as shown in FIG.
0, the polysilicon 31 is etched to form the gate oxide film 15 and the select gate 16.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, the case where the P-type silicon substrate is used is described. However, the N-type silicon substrate is used to inject holes,
The data may be stored by taking it out.

The same effect can be obtained by applying the present invention to a non-volatile memory device having an MNOS or MONOS memory transistor in which a floating gate is eliminated and charges are stored in a trap film. .
Further, as shown in Table 2, at the time of data writing, the select gates SGL2 and SGL3 are set to the ground potential 0V,
5 V is applied to the bit lines BL2, BL3, and BL4, the bit line BL1 is set to the ground potential 0 V, and the channel of the memory transistor is turned on with respect to the select gate line SGL1 in order to select a memory cell to which data is to be written. A marginal 1.5V may be applied and a high voltage 14V may be applied to the word lines WL1 and WL2. When erasing data, select gate SG
L1, SGL2, SGL3 and bit line BL3
BL4 is set at the ground potential of 0 V, and the bit line BL1 is opened (o
pen) state, 7V may be applied to the bit line BL2, and -6V may be applied to the word lines WL1 and WL2. Further, when data is read, select gates SGL2 and SGL3 and bit lines BL1 and BL
3, BL4 is set to the ground potential 0V, 5V is applied to the select gate SGL1, 2V is applied to the bit line BL2, and the sense is applied to the word lines WL1 and WL2 in order to select a memory cell to be read. A voltage of 3 V may be applied.

[0043]

[Table 2]

According to the above-described data writing method, data can be collectively written to the memory cells sharing the select gate line SGL1. Further, according to the data erasing method, the data stored in the memory cells sharing the bit lines BL1 and BL2 can be collectively erased. Furthermore, according to the data reading method,
The data stored in the memory cells sharing the select gate line SGL1 can be read at once.

[0045]

As is apparent from the above description, according to the present invention, a gradient of the surface potential is created between the charge storage layer and the select gate, and charges having high energy are efficiently generated in the channel region. Charges can be injected from the source region side of the charge storage layer.

As described above, by injecting charges from the source region side, the injection current between the charge storage layer and the select gate increases as the gate voltage increases, regardless of the current between the source region and the drain region. To keep growing,
There is an excellent effect that information can be written without reducing the speed.

[Brief description of the drawings]

FIG. 1 is a plan view of a nonvolatile memory according to one embodiment of the present invention.

FIG. 2 is a sectional view taken along line II of FIG.

FIG. 3 is an equivalent circuit diagram of a nonvolatile memory.

FIG. 4 is an explanatory diagram schematically showing an operation of a memory transistor at the time of writing data.

FIG. 5 is an explanatory diagram schematically showing an operation of a memory transistor when data is erased.

FIG. 6 is an explanatory diagram schematically showing an operation of a memory transistor when data is read.

FIG. 7 is a schematic sectional view showing a key process of the nonvolatile memory.

FIG. 8 is a perspective view showing a structure of a conventional nonvolatile memory.

FIG. 9 is an explanatory diagram schematically showing an operation of a memory transistor when data is written.

[Explanation of symbols]

MD1 nonvolatile memory MC11 memory cell MTr11, MTr12, MTr13, MTr14, M
Tr15, MTr16 memory transistor 11 P-type silicon substrate 12, 121, 122, 123, 124 LOCOS film 13, 131, 132, 133, 134 N ⁺ type buried impurity diffusion layer 13a Source region 13b Drain region 14 Channel region 15 Gate oxide film 16, 161, 162, 163 Select gate 17 Tunnel oxide film 181, 182, 183, 184, 185, 186 Floating gate 19 ONO film 201, 202 Control gate BL1, BL2, BL3, BL4 Bit line SGL1, SGL2, SGL3 Select gate Line WL1, WL2 Word line

Claims (2)

(57) [Claims] A plurality of nonvolatile memory elements for storing information by injecting and extracting electric charges on a single semiconductor substrate having a predetermined first conductivity type are provided in a row direction and a column direction. A plurality of LOCs thickly formed along the nonvolatile memory elements arranged in the column direction on the surface layer of the semiconductor substrate.
An OS insulating film and a bit line formed immediately below each LOCOS insulating film at predetermined intervals in the column direction and sharing a source region and a drain region between the nonvolatile memory elements adjacent in the row direction. And a buried impurity diffusion layer having a second conductivity type opposite to the first conductivity type, and a channel region formed between each of the buried impurity diffusion layers, which is formed on the source region side. A gate insulating film formed on a region to be determined; and a select gate line formed on each of the gate insulating films along the column direction and shared by the nonvolatile memory elements arranged in the column direction. A select gate is formed on each channel region except for the predetermined region on the source region side, and has high energy generated in each channel region. A tunnel insulating film having a thickness smaller than that of the gate insulating film, and a charge formed on each of the tunnel insulating films and storing the charge passing through the tunnel insulating film, and a source region thereof. A plurality of charge storage layers whose side ends cover a part of each of the select gates with an insulating film interposed therebetween; and a plurality of charge storage layers formed along the row direction on the respective charge storage layers and arranged in the row direction. A nonvolatile memory device comprising: a gate which is shared by nonvolatile memory elements and serves as a word line. 2. A method for writing information to a nonvolatile storage device according to claim 1, wherein said nonvolatile storage device is a nonvolatile storage device for writing information. A method for writing information in a nonvolatile memory device, wherein a low voltage is applied just before a channel of an element is turned on, and a high voltage is applied to a word line serving as a gate.