JPH06177393A - Nonvolatile storage device, its driving method, and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the stresses applied to tunnel insulating films so as to increase the number of rewriting times by forming gate insulating films having relatively thick thicknesses and the tunnel insulating films having thicknesses which are thinner than those of the gate insulating films in channel areas generated between adjacent buried impurity diffusion layers. CONSTITUTION:Gate oxide films 15 are formed in the areas 14 generated between each buried impurity diffusion layer 131, 132, and 133 except predetermined parts on drain areas 13b sides. Then tunnel oxide films 16 are formed in predetermined parts of the areas 14 on drain areas 13a sides. Then a trap nitride film 17 which stores charges is formed on the entire surface of this nonvolatile storage device including the films 15 and 16 and a block oxide film 18 which encloses the charges stored in the film 17 in the film 17 for a long time is formed on the film 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPROM (Ele
ctrically Erasable Programmable Read OnMemory)
The present invention relates to a nonvolatile memory device including a nonvolatile memory element that stores information by injecting and extracting charges, a driving method thereof, and a manufacturing method.

[0002]

2. Description of the Related Art Conventionally, a non-volatile memory element (hereinafter referred to as "memory transistor") that stores data by injecting and extracting charges on a single semiconductor substrate.
However, various non-volatile memory devices (hereinafter referred to as “non-volatile memory”) arranged in a matrix along the row direction and the column direction have been proposed.

An example of the above memory transistor is shown in FIG. FIG. 10 is a diagram schematically showing a schematic configuration of a conventional memory transistor. FIG. 10A is a data writing method, FIG. 10B is a data erasing method, and FIG. The respective reading methods are shown. This memory transistor is of a flash type and is shown in FIG.
As shown in (c), the P-type silicon substrate 1, the N ⁺ -type source region 2 and the N ⁺ -type drain region 3 and the source region 2 which are formed on the surface layer of the silicon substrate 1 with a predetermined gap.
And an ONO (oxide-nitride-o) formed on the channel region 4 which is formed so as to be sandwiched between the drain region 3 and the drain region 3 and accumulates charges having high energy generated in the channel region 4.
xide) film 5 and a gate 6 formed on the ONO film 5 and to which a control voltage is applied.

The ONO film 5 comprises a trap nitride film 5b made of Si ₃ N ₄ and a tunnel oxide film 5a made of SiO _2.
And has a sandwich structure sandwiched between the block oxide films 5c from above and below. The tunnel oxide film 5a has a function of tunneling charges having high energy generated in the channel region 4, the trap nitride film 5b has a function of accumulating charges tunneled through the tunnel oxide film 5a, and the block oxide film 5c has a function. , And has a function of trapping charges accumulated in the trap nitride film 5b for a long time.

Data writing, erasing, and reading operations of the memory transistor will be briefly described with reference to FIGS. <Writing> Data writing is performed by setting the source region 2 to the ground potential and the drain region 3 as shown in FIG.
Is applied to the gate 6 and 10 V is applied to the gate 6, and a high electric field is applied between the gate 6 and the drain region 3. A saturated channel current flows between the source region 2 and the drain region 3, so-called channel hot electrons generated by a high electric field are generated in the vicinity of the drain region 3, and the channel hot electrons are FN (Fowler-Nordheim) tunneled and drained. It is implanted into the trap nitride film 5b near the region 3. <Erase> To erase data, as shown in FIG.
The source region 2 is set to the ground potential, 9V is applied to the drain region 3, and -6V is applied to the gate 6. Gate 6-
Tunneling between bands between the drain regions 3 (band to b
and tunneling) causes hot holes to be injected from the drain region 3 into the trap nitride film 5b near the drain region 3. Then, the holes and the electrons accumulated in the trap nitride film 5b are electrically coupled and neutralized. <Read> To erase data, as shown in FIG. 10C, the source region 2 is set to the ground potential and the drain region 3 is set to 1
Data is stored in the memory transistor depending on whether the memory transistor is turned off or turned on by applying V to the gate 6 and applying a voltage 3 V which is an intermediate value between the threshold in the written state and the threshold in the erased state. Check the status.

[0006]

FIG. 11 shows the write / erase characteristics of the above memory transistor. In FIG. 11, the vertical axis represents both the threshold voltage of the threshold value in the read state and the drain current, and the horizontal axis represents the number of times of writing / erasing. As apparent from FIG. 11, in the memory transistor, as described above, since hot carriers are injected from the drain region side to locally write and erase data, the write / erase characteristics are Although the device is not deteriorated until the number of times (hereinafter, referred to as “the number of times of rewriting”) is about 1000 times, the erased state or the on-state characteristic is decreased after the number of times of rewriting reaches about 40,000 times. That is, when the number of times of rewriting reaches about 40,000 times, the difference between the threshold values due to writing and erasing (hereinafter, referred to as “memory window width”) gradually decreases. It is considered that this is because the number of traps in the tunnel oxide film increases due to the stress during writing and erasing. When the trap density becomes higher, the electric field due to the charges trapped in the trap becomes stronger, and the tunnel oxide film is degraded, resulting in poor retention.

Therefore, in order to reduce the stress applied to the tunnel oxide film, the source region 2 and the drain region 3 are left open as shown in FIGS. 12 (a) and 12 (b), and -15 V is applied to the gate 6. Then, a method of erasing the data can be considered. That is, as shown in FIG. 12A, a negative bias is applied between the gate 6 and the substrate 1, an FN (Fowler-Nordheim) tunnel current is generated from the substrate 1 toward the gate 6, and this FN tunnel current causes Holes are tunneled through the tunnel oxide film 5a from the entire channel region 4 and injected into the trap nitride film 5b. However, while erasing the electrons accumulated in the trap nitride film 5b in the vicinity of the drain region 3, FIG.
As shown in (b), the same amount of holes are injected into a region of the trap nitride film 5b where electrons have not been accumulated, resulting in a so-called over-erased state. Therefore, the erased state, that is, the threshold value of the initial memory transistor is changed, which is a problem in reliability.

In view of the above, the present invention can improve the number of times of rewriting by reducing the stress applied to the tunnel oxide film at the time of rewriting the data, and the reliable non-volatile memory in which over-erasing does not occur, and its driving method, And to provide a manufacturing method.

[0009]

A non-volatile memory device for achieving the above object is obtained by injecting or extracting charges on a single semiconductor substrate having a predetermined first conductivity type. A non-volatile memory device in which a plurality of non-volatile memory elements for storing information are arranged in a matrix along a row direction and a column direction, and arranged in a column direction on a surface layer of the semiconductor substrate. A plurality of LOCOS insulating films thickly formed along the nonvolatile memory element, and a source region and a drain between the nonvolatile memory elements formed along the column direction and directly adjacent to each other in the row direction immediately below each of the LOCOS insulating films. A plurality of buried impurity diffusion layers of the second conductivity type opposite to the first conductivity type, which are regions and bit lines extending in the column direction, are adjacent to each other. A relatively thick gate insulating film formed on a region except for a predetermined region on the drain region side of each channel region formed so as to be sandwiched by each buried impurity diffusion layer, and on the drain region side of each channel region. A tunnel insulating film, which is formed on a predetermined region and allows charges generated in each channel region to pass therethrough, which is relatively thinner than the gate insulating film, and which is formed on each of the gate insulating film and the tunnel insulating film. A charge storage layer that stores the electric charge that has passed therethrough, and a gate that is formed along the row direction on the charge storage layer and is shared by the nonvolatile memory elements arranged in the row direction and that serves as a word line are provided. It includes.

In the method for driving the non-volatile memory device, when writing information, the bit line including the source region of the non-volatile memory element in which the information is to be written is set to the ground potential and the bit line including the drain region is set. A high voltage is applied to a word line including a gate, and when erasing information, a bit line including a source region and a bit line including a drain region of a non-volatile memory element whose information is to be erased are respectively set. In the open state, a high voltage having a polarity different from that at the time of writing is applied to the word line including the gate, and at the time of reading information, the bit line stepping on the source region of the nonvolatile memory element from which information is read is set to the ground potential, A low voltage is applied to the bit line including the drain region, and a read voltage is applied to the word line including the gate. It is intended to pressure.

At the time of writing information, in the selected nonvolatile memory element, a high electric field is applied between the gate and drain regions, and a saturated channel current flows between the source and drain regions. As a result, high-energy charges are generated in the vicinity of the drain region, and these charges are FN tunneled through the tunnel insulating film and injected into the charge storage layer in the vicinity of the drain region, resulting in a written state.

At the time of erasing information, in the selected nonvolatile memory element, the tunnel insulating film is formed only on a predetermined region of the channel region on the drain region side, and the tunnel insulating film is formed on the remaining region more than the tunnel insulating film. Since the thick gate insulating film is formed, an FN tunnel current is generated from the substrate to the gate only in the channel region immediately below the tunnel insulating film, and this FN tunnel current has a polarity different from that at the time of writing from the drain region side of the channel region. Different charges are injected into the charge storage layer by tunneling through the tunnel insulating film. Then, the charge injected by the FN tunnel current and the charge stored in the charge storage layer are electrically coupled and neutralized,
The information is erased.

As described above, since the FN tunnel current injects charges having a polarity different from that at the time of writing to erase information, stress applied to the tunnel insulating film is reduced and the number of times of rewriting of information is increased. , The memory window width can be maintained in the initial state. Therefore, the number of times of rewriting can be improved. Further, since the FN tunnel current is generated only in the channel region directly below the tunnel insulating film,
While the charges accumulated in the charge storage layer near the drain region are being erased, no charge having a polarity different from that at the time of writing is injected into the region of the charge storage layer where the charges were not accumulated. Therefore, the overerased state does not occur and the reliability is improved.

If charges are stored in the charge storage layer of the selected nonvolatile memory element at the time of reading information, the influence of the gate charge extends to the surface of the semiconductor substrate immediately below the gate insulating film, but on the drain region side. The charges are canceled by the charges injected into the charge storage layer, and the influence of the charges does not reach the surface of the semiconductor substrate immediately below the tunnel insulating film. Therefore, a channel is not formed in the nonvolatile memory element, and no current flows. On the other hand, if no charge is stored in the charge storage layer of the selected nonvolatile memory element,
The influence of the gate charge extends to the surface of the semiconductor substrate immediately below the gate insulating film and the tunnel insulating film. Therefore, a channel is formed in the nonvolatile memory element and current flows.
If this state is sensed, the information stored in the nonvolatile storage element is read.

The method for manufacturing the above nonvolatile memory device comprises a step of sequentially forming a pad oxide film and a nitride film on a single semiconductor substrate having a predetermined first conductivity type, and a predetermined nitride film. A step of removing a part of the nitride film to expose the pad oxide film by leaving the region in a stripe shape along the column direction, using each nitride film left in a stripe shape along the column direction as a mask, A step of implanting impurity ions having a second conductivity type opposite to the first conductivity type, a pad oxide film is grown thick along the column direction by thermal oxidation to simultaneously form a plurality of LOCOS insulating films. Immediately below each LOCOS insulating film, it becomes a source region and a drain region of non-volatile memory elements adjacent to each other in the row direction in a self-aligned manner, and a bit line extending in the column direction. A step of forming a buried impurity diffusion layer of the second conductivity type; a step of forming a gate insulating film on a region sandwiched by the buried impurity diffusion layers by wet oxidation; a step of forming a gate insulating film on the drain region side in advance; A step of exposing a semiconductor substrate by applying a resist on a region other than a predetermined region and removing a predetermined region of the drain region side of the gate insulating film, and a drain region side where the semiconductor substrate is exposed after removing the resist Forming a tunnel insulating film thinner than the gate insulating film on a predetermined region of the above, forming a charge storage layer on each gate insulating film and tunnel insulating film, and on the charge storage layer in the row direction. This includes a step of forming a gate, which becomes a word line shared by the arranged nonvolatile memory elements, in the row direction.

As described above, by forming the buried impurity diffusion layer directly under the LOCOS insulating film before forming the gate, the channel length is not affected even if the position of the gate is deviated. Is unnecessary.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. 1 is a plan view showing a state in which a passivation film is peeled off in a nonvolatile memory according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line I-I of FIG. The structure of the nonvolatile memory MD according to the present embodiment will be described with reference to FIGS. 1 and 2.

The nonvolatile memory MD of this embodiment is a FAC.
A plurality of flash type memory transistors MTr1, MTr2, MTr3, MTr which are of E (Flash Array Contactless EEPROM) type and which store data by injecting and extracting charges on a single P-type silicon substrate 11.
4 are arranged and formed in a matrix along the row direction X and the column direction Y.

The surface layer of the P-type silicon substrate 11 has a row of columns.
Memory transistors MTr1 and MTr arranged in the direction Y
3 and MTr2, MTr4 along LOCOS (local
 oxidation of silicon) film 121, 122, 123
Is made. The LOCOS film 121 at the left end in FIG.
Directly below the memory transistors MT arranged in the column direction Y.
Source regions 13a of r1 and MTr3, that is, bit regions
N to be in BL1⁺Type buried impurity diffusion layer 131
Are formed along the column direction Y. Also, L at the right end
Immediately below the OCOS film 123, memories arranged in the column direction Y
Drain region 13 of the transistors MTr2 and MTr4
b, that is, N that becomes the bit line BL3⁺Type embedding
The impurity diffusion layer 133 is formed along the column direction Y.
It Further, directly below the LOCOS film 122, the column direction Y
Of the memory transistors MTr1 and MTr3 arranged in
Drain region 13b and memory transistor MTr
2, the source region 13a of MTr4, that is, the bit line
N that becomes BL2 ⁺The type buried impurity diffusion layer 132 is
Between the buried impurity diffusion layers 131 and 133 on both ends and a predetermined distance
It is formed along the column direction Y with a gap. That is,
Buried impurity diffusion layer 132 to be the bit line BL2
Is a memory transistor MTr adjacent to the row direction X.
1, MTr2 and memory transistors MTr3, MT
It is shared with r4.

Each embedded impurity diffusion layer 131, 132,
Channel regions 1 generated so as to be sandwiched between 133
4, a gate oxide film 15 is formed on each of the regions except the predetermined region on the drain region 13b side. In addition, the drain region 13a of each channel region 14
A tunnel oxide film 16 capable of tunneling charges generated in the channel region 14 is formed on each of the predetermined regions on the side.

A trap nitride film 17 for accumulating charges tunneled through each tunnel oxide film 17 is formed on the entire surface including each gate oxide film 15 and tunnel oxide film 16. The trap nitride film 1 is formed on the trap nitride film 17.
A block oxide film 18 is formed to confine the charge accumulated in 7 for a long time.

Memory transistors M arranged in the row direction X
A gate 191 serving as a word line WL1 is formed along the row direction X on the block oxide film 18 in the formation region of Tr1 and MTr2. Further, a gate 192 serving as a word line WL2 is formed along the column direction X on the block oxide film 18 in the formation region of the memory transistors MTr13 and MTr4 arranged in the row direction X. That is, the gate 191 serving as the word line WL1 has the memory transistors MT arranged in the row direction X.
The gate 192, which is shared by r1 and MTr2 and serves as the word line WL2, is shared by the memory transistors MTr3 and MTr4 arranged in the row direction X.

Further, the buried impurity diffusion layers 131 and 13
2, 133, and the surface layer of the silicon substrate 11 surrounded by the gates 191 and 192, the memory transistors MT which are adjacent to each other in the column direction Y as indicated by a mark X in FIG.
r1, MTr3 and memory transistors MTr2, M
Channel stop ions are implanted for element isolation of Tr4.

In the following description, the memory transistors MTr1, MTr2, MTr3, MTr4 are collectively referred to as "memory transistor MTr". Further, the LOCOS films 121, 122, and 123 are collectively referred to as “LOCOS film 12” and the embedded impurity diffusion layer 1.
When referring to 31, 132 and 133 collectively, it is referred to as “embedded impurity diffusion layer 13”, and when referring to the gates 191 and 192, it is referred to as “gate 19”.

The P-type silicon substrate 11 has a specific resistance of 5 to 2
As low as 0 Ωcm is used. LOCO
The S film 12 is made of SiO ₂ and has a film thickness of about 10000Å
It is provided to be thick. The gate oxide film 15 is made of Si
It is made of O ₂ and has a thin film thickness of about 300 Å.

The trap nitride film 17 is made of Si ₃ N ₄ , and its film thickness is set to a predetermined thickness so as to accumulate charges. The block oxide film 18 is made of SiO ₂ , and its film thickness is set to a predetermined thickness so as to confine charges in the trap nitride film 17. The gate 19 is made of, for example, a conductive material such as polysilicon which is doped with phosphorus at a high concentration to reduce the resistance.

Further, although not shown, in order to protect the surface of the memory transistor MTr on the entire surface of the gate 19 and prevent invasion of contaminants from the outside, passivation made of an insulating material such as PSG is used. Membranes are stacked. As described above, the non-volatile memory MD is a so-called virtual ground array that does not make contact with the buried impurity diffusion layer 13 on the silicon substrate 11, thereby achieving high-density mounting of the memory transistors MTr. ing.

FIG. 3 is an equivalent circuit diagram of the non-volatile memory. The electrical configuration of the nonvolatile memory MD will be described with reference to FIG. The nonvolatile memory MD is shown in FIG.
, The memory cells MC1, MC2, M surrounded by the one-dot chain line
C3 and MC4 are arranged and each memory cell MC1 and MC
2, MC3 and MC4 are one memory transistor MTr
1 cell / 1 consisting of 1, MTr2, MTr3, MTr4
It has a transistor structure.

Then, the word lines W are connected to the gates of the memory transistors MTr1 and MTr2 arranged in the row direction X.
The word line WL2 is connected to the gates of the memory transistors MTr3 and MTr4 connected to the row direction X and arranged in the row direction X.
Are connected. The bit line BL1 is connected to the sources of the memory transistors MTr1 and MTr3 arranged in the column direction Y, and the bit line BL is connected to the drains of the memory transistors MTr2 and MTr4 arranged in the column direction Y.
3 are connected. Then, the memory transistors MTr1, MTr2 and MTr adjacent to each other in the row direction X
3, the source and drain of MTr4 are connected in series, and the bit line BL2 is connected to the connection intermediate point.

Now, the data writing, erasing and reading operations of the non-volatile memory MD10 will be described mainly with reference to FIG. 3 and Table 1. In Table 1, it is assumed that the memory cell MC1 shown in FIG. 3 is selected when writing and reading data.

[0031]

[Table 1]

<Write> The word line WL2 is set to the ground potential 0V, and the bit line BL3 is set to 9V.
Is applied to write data into the memory cell M.
To select C1, set the bit line BL1 to ground potential 0V.
Then, 9V is applied to the bit line BL2 and 10V is applied to the word line WL1.

Then, as shown in FIG. 4, in the memory transistor MTr1 in the selected memory cell MC1, a high electric field is applied between the gate 191 and the drain region 13a, and the saturated channel current flows between the source region 13a and the drain region 13b. Flows. In the pinch off region near the drain region 13a, electrons accelerated by a high electric field cause ionization (impact ionization),
Channel hot electrons having high energy are generated, the channel hot electrons are FN tunneled through the tunnel oxide film 16 and injected into the trap nitride film 17 in the vicinity of the drain region 13b, and a data "1" write state is set.

On the other hand, in the memory transistor in the non-selected memory cell, a high electric field is not applied between the gate region and the drain region, and a saturated channel current does not flow between the source region and the drain region. Electrons are not injected. That is, no data is written. The gate voltage required to establish conduction between the source and drain of the memory transistor changes depending on whether electrons are accumulated in the trap nitride film or not. That is, the threshold voltage V _TH for making the source-drain of the memory transistor conductive is a high threshold V1 (for example, 4 V) when electrons are injected into the floating gate.
Therefore, a low threshold value V2 (for example, 0.5 V) is set in a state where electrons are not injected. in this way,
By setting the threshold voltage V _TH to two types, binary data “1” or “0” can be stored in the memory transistor. <Erase> Data is erased by batch erasing. That is, the bit lines BL1, BL2BL3 are left open, and the word lines WL1, WL2 are
Apply 15 V and apply a negative bias between the gate and the substrate.

Then, as shown in FIG. 5, in the memory transistor MTr in each memory cell, the tunnel oxide film 16 is formed only on the predetermined region of the channel region 14 on the drain region 13b side, and the remaining region is formed. Since the gate oxide film 15 which is thicker than the tunnel oxide film 16 is formed on the gate oxide film 16, only the channel region 14 directly below the tunnel oxide film 16 is exposed from the substrate 11 toward the gate 19 with F.
An N tunnel current is generated, and the FN tunnel current causes holes to be injected into the trap nitride film 17 from the drain region 13b side of the channel region 14 through the tunnel oxide film 16. Then, the holes injected by the FN tunnel current and the electrons accumulated in the trap nitride film 17 are electrically coupled and neutralized, and the erased state of data,
That is, the data "0" is written.

Since data is erased by injecting holes by the FN tunnel current as described above, the stress applied to the tunnel oxide film 15 is reduced, and even if the number of times of rewriting data is increased, the memory window width is initially set. Can be maintained as is. Therefore, the number of times of rewriting can be improved. In addition, the FN tunnel current is the tunnel oxide film 16
Since it occurs only in the channel region 14 immediately below, the trap nitride film 17 is erased while the electrons accumulated in the trap nitride film 17 near the drain region 13b are being erased.
The holes are not injected into the region where the electrons were not accumulated. Therefore, the overerased state does not occur and the reliability is improved. <Read (READE)> The word line WL2 is set to the ground potential 0V, 1V is applied to the bit line BL3 in advance, the bit line BL1 is set to the ground potential 0V, and the bit line BL2 is set to select the memory cell MC1 to be read. 1V to the word line WL1
A sense voltage of 2V is applied to.

At this time, as shown in FIG. 6A, if electrons are accumulated in the trap nitride film 17 of the memory transistor MTr1 of the memory cell MC1, the influence of the positive charge of the gate 191 is directly below the gate oxide film 15. However, the positive charges on the drain region 13b side are canceled by the electrons injected into the trap nitride film 17, and the influence of the positive charges on the silicon substrate 11 immediately below the tunnel oxide film 16 is affected. Does not reach the surface. Therefore, no channel is formed in the memory transistor MTr1 and no current flows from the drain region 13b of the embedded impurity diffusion layer 132 to the source region 13a of the embedded impurity diffusion layer 131. On the other hand, FIG. 6 (b)
As shown in FIG. 3, if electrons are not accumulated in the trap nitride film 17, the positive charge of the gate 191 affects the surface of the silicon substrate 11 directly below the gate oxide film 15 and the tunnel oxide film 16. Therefore, a channel is formed in the memory transistor MTr1 and a current flows from the drain region 13b of the embedded impurity diffusion layer 132 to the source region 13a of the embedded impurity diffusion layer 131. If this state is sensed by a decoder and a sense amplifier (not shown), the data stored in the memory transistor MTr1 is read.

Here, the sense voltage is an intermediate voltage between two types of V1 and V2 of the above threshold voltage V _TH .
Therefore, when this sense voltage is applied, conduction / non-conduction of the memory transistor is determined by whether or not electrons are accumulated in the trap nitride film. 7 to 8 are schematic cross-sectional views showing a method of manufacturing a nonvolatile memory in the order of steps. 7 to 8, only one memory transistor is shown for convenience of description.

First, a LOCOS film and a buried impurity diffusion layer are formed. That is, as shown in FIG. 7A, the P-type silicon substrate 11 is thermally oxidized at about 900 to 1000 ° C. to form a pad oxide film 30 of about 1000 Å, and then nitrided by a CVD (Chemicai Vapor Deposition) method. A silicon (Si ₃ N ₄ ) film 31 is formed. Then, as shown in FIG. 7B, the silicon nitride film 31 is removed by etching to expose the pad oxide film 30 by leaving a predetermined region of the silicon nitride film 31 in a stripe shape along the column direction. . The remaining silicon nitride film 31 becomes a formation region of a memory transistor to be formed. For this etching, CF ₄ /
O ₂ plasma etching is preferred.

Next, as shown in FIG. 7C, N ⁺ -type impurity ions such as As ⁺ are implanted using the silicon nitride film 31 left in stripes along the column direction as a mask. After that, as shown in FIG. 7D, the silicon substrate 11 is oxidized in a water vapor (H ₂ O) atmosphere at about 1000 ° C. for about 6 to 7 hours, and the pad oxide film 31 is about 10,000 Å along the column direction. LOCOS
The film 12 is formed. At the same time, the source region 13a and the drain region 1 are formed directly below the LOCOS film 12 between the memory transistors adjacent to each other in the row direction in a self-aligned manner.
N ⁺ -type buried impurity diffusion layers 13 that share 3b and serve as bit lines are formed along the column direction. Here, the reason why wet oxidation using H ₂ O is used instead of dry oxidation is that the oxidation rate is large and the oxidation time can be shortened. Since the silicon nitride film 31 serves as a barrier against diffusion of the oxidizer (H ₂ O), the pad oxide film 31 in the portion covered with the silicon nitride film 31 does not grow.

When the steps of forming the LOCOS film and the buried impurity diffusion layer are completed, a gate oxide film and a tunnel oxide film are formed. That is, as shown in FIG. 8A, the remaining silicon nitride film 31 and the pad oxide film 30 thereunder are sequentially removed. Then, as shown in FIG. 8B, the surface of the silicon substrate 11 exposed in the step of FIG. 8A by oxidizing the silicon substrate 11 in a steam atmosphere at about 900 to 1000 ° C. for about 1 hour, That is, a thin gate oxide film 15 of about 300 Å is formed on the channel region 14 which is formed so as to be sandwiched between the buried impurity diffusion layers 13. At this time, both ends of the gate oxide film 15 are LOC.
Connect to the bird's beak of the OS film 12.

Next, as shown in FIG. 8C, a resist pattern 32 is formed on a region of the gate oxide film 15 other than a predetermined region on the drain region b side, and the drain region of the gate oxide film 15 is formed. A predetermined region on the side of 13a is removed by etching to expose the surface of the silicon substrate 11.
It is preferable to use RIE (reactive ion etching) for this etching. Because the resist pattern 3
This is because two types of etching processing can be performed.

[0043] Thereafter, as shown in FIG. 8 (d), the O ₂ about the silicon substrate 11 to about 800 ° C. in N ₂ 1/100
The surface of the silicon substrate 11 exposed in the step of FIG. 8C and the predetermined region on the side of the drain region 13a of the channel region 14 exposed in the step of FIG. A thin tunnel oxide film 16 is formed.

When the steps of forming the gate oxide film and the tunnel oxide film are completed, a charge storage layer is formed. That is, as shown in FIG. 9A, LPCVD (Low Pressurization
by e Chemicai Vapor Deposition) method, Si ₃ on the whole surface
N ₄ is deposited to a thickness of about 200Å to form a trap nitride film 17
To form. Then, as shown in FIG. 9B, wet oxidation is performed for about 3 hours. Then, the upper layer portion of the trap nitride film 17, which is thickly deposited in advance, is eroded by O ₂ , and the block oxide film 18 is formed on the trap nitride film 17.

When the above charge storage layer forming step is completed, a metallization and passivation film is formed. That is, as shown in FIG. 9C, polysilicon is deposited on the entire surface by sputtering or the like, and a conductive substance such as phosphorus is doped at a high concentration. After that, this polysilicon is patterned in a stripe shape along the row direction,
The gate 19 is formed. Subsequently, the passivation film 33 is formed by depositing silicon nitride or the like on the entire surface by the CVD method.
To form.

Thus, the impurity diffusion layer is not formed by ion implantation using the gate as a mask, but the buried impurity diffusion layer 13 is formed directly under the LOCOS film 12 before the gate 19 is formed. , Gate 19
Even if the position of is shifted, it does not affect the channel length. Therefore, the alignment of the gate 19 becomes unnecessary.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, the case where the P-type silicon substrate is used is described, but the N-type silicon substrate may be used. In addition, as shown in Table 2, when writing data, the bit line BL
In order to select a memory cell in which data is to be written, 9V is applied to 3 and the bit line BL1 is set to the ground potential 0V, 9V is applied to the bit line BL2, and the word lines WL1 and WL2 are applied. 10V may be applied. In addition, at the time of reading data, 1V is applied to the bit line BL3 in advance, the bit line BL1 is set to the ground potential 0V, and 1V is applied to the bit line BL2 in order to select a memory cell to be read. Sense voltage 2 for word lines WL1 and WL2
V may be applied.

[0048]

[Table 2]

According to the above-described data writing method, data can be written in a line batch to the memory cells sharing the bit lines BL1 and BL2. According to the data read method, the bit lines BL1 and BL2
The data stored in the memory cells that share the line can be read in batch.

[0050]

As is apparent from the above description, according to the present invention, the stress applied to the tunnel insulating film at the time of rewriting information can be reduced, so that the number of times of rewriting can be improved. Moreover, reliability is improved because over-erasing does not occur.

[Brief description of drawings]

FIG. 1 is a plan view of a nonvolatile memory according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II of FIG.

FIG. 3 is an equivalent circuit diagram of a nonvolatile memory.

FIG. 4 is an explanatory diagram schematically showing the operation of the memory transistor at the time of writing data.

FIG. 5 is an explanatory diagram schematically showing the operation of the memory transistor when erasing data.

FIG. 6 is an explanatory diagram schematically showing the operation of the memory transistor when reading data.

FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory in the order of steps.

FIG. 8 is a schematic cross-sectional view showing the manufacturing method in order of steps, continuing from FIG.

FIG. 9 is a schematic cross-sectional view showing the manufacturing method following FIG. 8 in order of steps.

FIG. 10 is a diagram schematically showing a schematic configuration of a memory transistor used in a conventional nonvolatile memory.

FIG. 11 is a diagram showing write / erase characteristics of a memory transistor.

FIG. 12 is an explanatory diagram schematically showing the operation of the memory transistor when data is erased by an FN tunnel.

[Explanation of symbols]

MD non-volatile memory MC1, MC2, MC3, MC4 memory cell MTr, MTr1, MTr2, MTr3, MTr4 memory transistor 11 P type silicon substrate 12, 121, 122, 123 LOCOS film 13, 131, 132, 133 N ⁺ type buried impurity Diffusion layer 13a Source region 13b Drain region 14 Channel region 15 Gate oxide film 16 Tunnel oxide film 17 Trap nitride film 19 Block oxide film 19 Gate BL1, BL2, BL3, BL4 Bit line WL1, WL2 Word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11B 5/024 9196-5D G11C 17/00 6741-5L H01L 21/318 B 7352-4M 27/115

Claims (3)

[Claims] 1. A plurality of non-volatile storage elements for storing information by injecting and extracting charges on a single semiconductor substrate having a predetermined first conductivity type are arranged in a row direction and a column direction. A plurality of LOCs formed thickly along the nonvolatile memory elements arranged in the column direction on the surface layer of the semiconductor substrate.
An OS insulating film, which is formed immediately below each of the LOCOS insulating films and which is formed along the column direction, serves as a source region and a drain region of adjacent nonvolatile memory elements adjacent to each other in the row direction, and serves as a bit line extending in the column direction. , A plurality of buried impurity diffusion layers having a second conductivity type opposite to the first conductivity type, and a predetermined predetermined drain region side of a channel region formed so as to be sandwiched between adjacent buried impurity diffusion layers. A relatively thick gate insulating film formed on a region other than the region, a gate insulating film formed on a predetermined region on the drain region side of each of the above-mentioned channel regions and allowing charges generated in each channel region to pass therethrough. Also a relatively thin tunnel insulating film, charges formed on the gate insulating film and the tunnel insulating film, and passing through the tunnel insulating film. And a gate which is formed along the row direction on the charge storage layer and is shared by the nonvolatile memory elements arranged in the row direction to form a word line. Non-volatile storage device. 2. A method for driving a non-volatile memory device according to claim 1, wherein a bit line including a source region of a non-volatile memory element in which information is to be written is set to a ground potential when writing information.
A high voltage is applied to the bit line including the drain region, a high voltage is applied to the word line including the gate, and at the time of erasing information, the bit line including the source region of the non-volatile memory element from which information should be erased. The bit line including the drain region and the drain region is opened, and a high voltage with a polarity different from that during writing is applied to the word line including the gate. When reading information, the source region of the nonvolatile memory element from which information should be read Set the bit line stepping on to the ground potential,
A method of driving a nonvolatile memory device, comprising applying a low voltage to a bit line including a drain region and a read voltage to a word line including a gate. 3. A method for manufacturing a non-volatile memory device according to claim 1, wherein a pad oxide film and a nitride film are sequentially formed on a single semiconductor substrate having a predetermined first conductivity type. Step, leaving a predetermined region of the nitride film in a stripe shape along the column direction, removing a part of the nitride film to expose the pad oxide film, and leaving it in a stripe shape along the column direction. And a step of implanting impurity ions having a second conductivity type opposite to the first conductivity type using each nitride film as a mask, and a pad oxide film is grown thickly along the column direction by thermal oxidation. Simultaneously with the formation of the LOCOS insulating film, the non-volatile memory elements adjacent to each other in the row direction become source regions and drain regions in a self-aligning manner immediately below each LOCOS insulating film and extend in the column direction. A step of forming a buried impurity diffusion layer of the second conductivity type to be a bit line, a step of forming a gate insulating film on a region sandwiched by the buried impurity diffusion layers by wet oxidation, A step of exposing a semiconductor substrate by applying a resist to a region other than a predetermined region on the drain region side and removing a predetermined region of the gate insulating film on the drain region side, after exposing the semiconductor substrate after removing the resist Forming a tunnel insulating film thinner than the gate insulating film on a predetermined region on the drain region side, forming a charge storage layer on each gate insulating film and tunnel insulating film, and on the charge storage layer In addition, the method includes a step of forming along the row direction gates which are word lines shared by the nonvolatile memory elements arranged in the row direction. And a method for manufacturing a non-volatile memory device.