JP3426641B2 - Nonvolatile storage element, nonvolatile storage device using the same, and method of driving this storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory element, a non-volatile memory device using the same, and a driving method of the memory device.

[0002]

2. Description of the Related Art In recent years, with the development of the semiconductor industry, there has been a demand for integration of non-volatile memory devices which semi-permanently store information. In order to meet this demand, it is possible to improve the degree of integration of the memory cell circuit. Therefore, conventionally, a nonvolatile memory device having a one-transistor / one-cell structure has been proposed. FIG. 10 is an equivalent circuit diagram showing an electrical configuration of a conventional nonvolatile memory device. The nonvolatile memory device, as shown in FIG. 10, the memory transistor 1A that having a floating gate FG, 1B, 1
Memory cells 2A, 2B, 2C, 2 consisting only of C and 1D
Ds are arranged in a matrix along the row direction X and the column direction Y.

In the control gates of the memory transistors 1A, 1B and 1C, 1D in the memory cells 2A, 2B and 2C, 2D arranged along the row direction X,
The word lines WL1 and WL2 are connected to each other, and the memory cells 2A arranged in the column direction Y are arranged.
Memory transistors 1A, 1 in 2C and 2B, 2D
The bit line BL is connected to the drains of C, 1B and 1D.
1 and BL2 are respectively connected. Further, the source of the memory transistors 1A, 1B, 1C and 1D in each of the memory cells 2A, 2B, 2C and 2D is the source line S.
However, the substrate lines SUB are commonly connected to the substrates.

An information writing operation in the nonvolatile memory will be described with reference to FIG. For example, assume that information is written in the memory cell 2A. 0 V is applied to the source line S and the substrate line SUB in advance, 10 V is applied to the word line WL1 to which the memory cell 2A is connected, and the memory cell 2A is connected to select the memory cell 2A. 6V is applied to the existing bit line BL1. On the other hand, the word line WL to which the non-selected memory cells 2C and 2D are connected
0V is applied to 2 and non-selected memory cells 2B and 2D
0V is applied to the bit line BL 2 to which is connected.

Then, charges are injected into the floating gate FG of the memory transistor 1A in the memory cell 2A, and the memory cell 2A is in a state of writing information. In the following description, the memory transistors 1A, 1
B, 1C and 1D are collectively referred to as "memory transistor 1". FIG. 11 is a schematic sectional view showing the structure of the memory transistor. Referring to FIG. 1, the memory transistor 1 includes a P-type silicon substrate 10 and a silicon substrate 1
It is formed on the N ⁺ type source region 10b and the N ⁺ type drain region 10c which are formed in the surface layer of 0 at a predetermined interval, and the channel region 10a which is formed so as to be sandwiched between the source region 10b and the drain region 10c. The tunnel oxide film 11, the floating gate 12 formed on the tunnel oxide film 11, the ONO (oxide nitride oxide) film 13 formed on the floating gate 12,
And a control gate 14 formed on the NO film 13.

At the time of writing information, 0V is applied to the source region 10b of the memory transistor 1 and the substrate 10 respectively, and 10V is applied to the control gate 14.
When 6V is applied to the drain region 10c,
A saturated channel current flows between the source and drain. A pinch off region (pinch off reg) near the drain region 10c
In ion, the electrons accelerated by the high electric field are ionized (imp
electron, which has high energy,
So-called hot electrons are generated. The hot electrons tunnel through the tunnel oxide film 11 and are injected into the floating gate 12. As a result, writing of information is achieved.

[0007]

In the above non-volatile memory device, when writing information, electrons are injected into the floating gate of the memory transistor. At this time, the write current is increased to cause the accelerated electrons to collide with silicon in the vicinity of the drain to generate hot electrons, and the hot electrons are locally injected into the floating gate. Therefore, the tunnel oxide film is locally deteriorated, leading to a decrease in the number of rewrites.

Further, since it is a local write, it takes a long time for electrons to be accumulated in the entire floating gate, and information cannot be written instantaneously. Further, at the time of writing, a write disturb may occur in a non-selected memory cell. For example, in FIG. 10, when the memory cell 2A is selected at the time of writing, the unselected memory cell 2C sharing the bit line BL1 is connected to the control gate 14 of the memory transistor 1C as shown in FIG. 0V is applied to the drain region 10c, and 6V is applied to the drain region 10c.
isturb) occurs. That is, the memory transistor 1
When the information in which electrons are accumulated in the floating gate 12 of C is written, the electrons accumulated in the floating gate 12 are drained.
It is pulled out to 0c. As a result, the memory transistor 1
The information written in C is destroyed.

On the other hand, in the non-selected memory cell 2B sharing the word line WL1 with the selected memory cell 2A, as shown in FIG.
10V for control gate 14 and 0V for substrate 10
Is applied, so-called gate disturb
(gate disturb) occurs. That is, when the floating gate 12 of the memory transistor 1B is in the erased state of information in which electrons are not accumulated, the substrate 10-
Due to the potential difference between the control gates 14, the FN (Fowle
r-Nordheim) tunnel current is generated, and electrons are injected into the floating gate 12 by this FN tunnel current. As a result, information is erroneously written in the memory transistor 1B.

In view of the above, the present invention can increase the number of rewritable times. Information can be rewritten instantly. It is possible to prevent write disturb when writing information. It is an object of the present invention to provide a non-volatile memory element capable of performing the above, a non-volatile memory device using the same, a method of driving the memory device, and a method of manufacturing the memory element.

[0011]

The non-volatile memory element of the present invention for achieving the above object stores information by injecting and extracting electric charges, and is predetermined. that a semiconductor substrate in which the conductive type guide, a source region and a drain region formed at predetermined intervals in the surface layer of the semiconductor substrate, to the source and drain regions on a channel region sandwiched by as occurs in, A tunnel insulating film formed at a predetermined offset distance from the source region and capable of tunneling charges generated in the channel region, and a floating gate formed on the tunnel insulating film and storing charges tunneled through the tunnel insulating film. And a capacitor insulating film formed on the floating gate to confine charges in the floating gate. Is formed on the capacitor insulating film, a control gate predetermined control voltage is applied, together with in contact with the source region, reading of information
When a read voltage is applied at the time of protrusion, the source area above
A channel region between the band and the tunnel insulating film O
As you can reverse the offset region, a floating gate, an insulating state relative capacitor insulating film and a control gate, an insulating film on the offset region
And a source electrode that is extended.

In the nonvolatile memory device using the nonvolatile memory element, the nonvolatile memory elements are arranged and formed in a matrix on the semiconductor substrate along the row direction and the column direction, and along the row direction. The word lines are connected to the control gates of the non-volatile memory elements arranged in a row, and the bit lines are connected to the drain regions of the non-volatile memory elements arranged along the column direction. A source line of a device is commonly connected to a source line, and a semiconductor substrate is provided with a common substrate line.

In the above method for driving the nonvolatile memory device, the source line and the substrate line are set to the ground potential at the time of writing information, and the word line connected to the nonvolatile memory element for writing is connected to the ground potential. semiconductor
FN tunnel current between substrate and floating gate
It applies a high voltage may cause, otherwise
The word line and the ground potential, for selecting the nonvolatile memory element for writing, for the other bit lines together with the non-volatile storage elements to apply a write voltage to the bit line connected Write inhibit voltage
Is applied to generate an FN tunnel current between the substrate and the floating gate of the selected nonvolatile memory element, the FN tunnel current injects charges into the floating gate, and when erasing information, all bit lines and leave the source line and an open state, the word line non-volatile memory device for erasing the information is connected to ground potential, and the semiconductor substrate relative to the substrate line
FN tunnel current is generated between floating gate
Applying a high voltage capable of, the substrate of the selected nonvolatile memory element - caused the FN tunnel current in the direction opposite to that in the writing between the floating gates, the charge stored in the floating gate by the FN tunnel current To the substrate side, at the time of reading information, the substrate line is set to the ground potential, and a read voltage capable of inverting the substrate surface in the offset region is applied to the source line, and the nonvolatile memory element for reading is connected. The bit line connected to the nonvolatile memory element is set to the ground potential in order to apply the sense voltage to the selected word line and select the nonvolatile memory element for reading.

When writing the above information, the channel regions between the floating gates and the source regions of all the non-volatile memory elements are always offset regions. Substrate in this case, the selected nonvolatile memory element - Floating
FN tunneling current is generated between the ring gate, charge is injected into the floating gate by the FN tunnel current. Further, the non-selected non-volatile storage element sharing the bit line with the selected non-volatile storage element does not operate. Therefore, drain disturb does not occur in the non-selected nonvolatile memory element. Further, between the substrate and the control gate of the nonvolatile memory element that shares the word line with the selected nonvolatile memory element,
Although a potential difference occurs, the depletion layer at the PN junction of the drain region spreads to the boundary of the offset region, and this depletion layer blocks the FN tunnel current. Therefore, charges are not injected into the floating gate due to the FN tunnel current. Therefore, the gate disturb does not occur in the non-selected nonvolatile memory element.

At the time of erasing information, a bias reverse to that at the time of writing is applied between the substrate and the control gate of the selected nonvolatile memory element, and the electric charge accumulated in the floating gate escapes to the substrate side by the FN tunnel current. . As described above, since the information is rewritten by the FN tunnel current, the deterioration of the tunnel insulating film can be prevented and the number of rewritable times can be increased.
Data can be rewritten instantly.

At the time of reading, the substrate surface in the offset regions of all the non-volatile memory elements is inverted and an inversion layer is formed. At this time, if charges are accumulated in the selected nonvolatile memory element, the influence of the positive charges of the control gate is blocked by the charges accumulated in the floating gate, and does not reach the surface of the substrate directly below the floating gate. As a result, the source region and the drain region of the nonvolatile memory element are not electrically connected to each other and a channel is not formed. That is, no current flows in the nonvolatile memory element. On the other hand, if no charge is stored in the floating gate of the selected nonvolatile memory element, the influence of the positive charge of the control gate extends to the surface of the substrate immediately below the floating gate and the surface of this substrate is inverted. As a result, conduction is established between the source region and the drain region of the nonvolatile memory element, and a channel is formed. That is, a current flows in the nonvolatile memory element. Reading of information is achieved by sensing this state.

As described above, since the information is read by utilizing the inversion of the offset area, the reading speed becomes high.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing the structure of a nonvolatile memory element according to an embodiment of the present invention, showing a state in which a passivation film is peeled off. The configuration of the nonvolatile memory element according to the present embodiment will be described with reference to FIG.

As shown in FIG. 1, the nonvolatile memory element of this embodiment has a P-type silicon substrate 30 and a silicon substrate 30.
The source region 30b is formed on the N ⁺ -type source region 30b and the N ⁺ -type drain region 30c which are formed in the surface layer of the device at a predetermined interval, and the channel region 30a which is formed so as to be sandwiched between the source region 30b and the drain region 30c. And a tunnel oxide film 31 formed with a predetermined offset distance D, a floating gate 32 formed on the tunnel oxide film 31, a capacitor insulating film 33 formed on the floating gate 32, and a capacitor insulating film 3
Control gate 34 (WL) formed on
A source electrode 40 that is in contact with the source region 30b and extends over the remaining region of the channel region 30a, injects charges into the floating gate 32,
Information is stored by taking it out.

The tunnel oxide film 31 is formed in the channel region 30.
The charge generated in a can be tunneled. Therefore, the tunnel oxide film 31 is made of SiO ₂ , and its film thickness is extremely thin so that the charges can be tunneled. The floating gate 32 is made of, for example, polysilicon that is doped with phosphorus at a high concentration to reduce the resistance.

The capacitor insulating film 33 keeps charges in the floating gate 32 for a long time.
Therefore, the capacitor insulating film 33 is a so-called ONO in which a Si ₃ N ₄ film is sandwiched between upper and lower SiO ₂ films.
It has a (oxide nitride oxide) structure. Hereinafter, the capacitor insulating film 33 will be referred to as “ONO film 33”. Like the floating gate 32, the control gate 34 is made of, for example, polysilicon in which phosphorus is doped at a high concentration to reduce the resistance.

The source electrode 40 is made of a conductive material such as tungsten polycide. Between the source electrode 40 and the channel region 30a, and the source electrode 40,
An oxide insulating film 35 is interposed between the floating gate 32, the ONO film 33, and the control gate 34 and the source region 30b side. This oxide insulating film 35
Is made of SiO ₂ .

The entire surface is BPSG (boron phosfied si
It is covered with an interlayer insulating film 36 made of licon glass). Therefore, the floating gate 32 is not connected to the outside. Drain region 3 of interlayer insulating film 36
A contact hole 37 is opened in a portion corresponding to 0c. Al− through this contact hole 37
A bit line 38 (BL) made of Si or the like is in contact.

2 and 3 show the manufacturing of a non-volatile memory element.
It is a schematic sectional drawing which shows a manufacturing method in order of a process. Figure 2 and Figure
3, the method for manufacturing the nonvolatile memory element will be described.
And explain. First, the gate is formed. That is,
As shown in FIG. 2 (a), P-type silicon is formed by thermal oxidation.
SiO 2 on the substrate 30 with a film thickness of 100 Å₂From
A tunnel oxide film 31 is formed. After that, Figure 2
As shown in (b), for example, LPCVD (low pressure
Chemical vapor deposition) method, tunnel oxide film
After depositing the polysilicon film 40 on the surface 31,
In order to supply the polysilicon film 40 with phosphorus,
To do. Next, as shown in FIG. 2C, a polysilicon film
40, for example SiO₂About 60Å, Si₃N_FourTo
110Å, SiO ₂ON by sequentially stacking about 60Å
The O film 33 is formed. After that, as shown in FIG.
In addition, the poly on the ONO film 33 is formed by LPCVD, for example.
After depositing the silicon film 41, in order to impart conductivity,
The polysilicon film 41 is doped with phosphorus. That
Then, as shown in FIG.
The polysilicon film 41,
ONO film 33, polysilicon film 40, and tunnel oxidation
The film 31 is removed to remove the floating gate 32 and
The control gate 34 (WL) is formed.

When the above gate forming step is completed, a source region and a drain region are formed. That is, FIG.
As shown in (a), a thin SiO ₂ film is grown by thermal oxidation, and the tunnel oxide film 31, the floating gate 32, the ONO film 33, and the control gate 34 are surrounded by an oxide insulating film 35. The thickness of the oxide insulating film 35 is preferably about 300 Å, for example. Next, FIG. 3 (b)
As shown in FIG.
3 and one side of the control gate 34 (left side in the drawing) is coated with a resist 42 for forming the offset interval. Subsequently, using the resist 42 and the floating gate 32, the ONO film 33, the control gate 34, and the side wall gate 39 as a mask, phosphorus is ion-implanted by, for example, implantation to implant N on the surface layer of the P-type silicon substrate 30. ^{The +} type source region 30b and the N ⁺ type drain region 30c are formed in a self-aligned manner. In this step, the offset distance between the floating gate 32 and the source region 30b is controlled by the width of the resist 42, and the distance is 0.2 to 0.3.
About μm is preferable.

When the process of forming the source region and the drain region is completed, the source electrode is formed. That is,
As shown in FIG. 3C, after forming an opening in a portion of the oxide insulating film 35 corresponding to the source region 30b, for example, PVD is used.
A tungsten polycide is deposited by the (physical vapor deposition) method to form the source electrode 40 in the source region 3
It is formed by contacting with 0b and extending to the offset region.

When the source electrode forming step is completed, an interlayer insulating film is formed and metallization is performed. That is, as shown in FIG. 3D, BPSG is deposited on the entire surface by, eg, CVD method to form the interlayer insulating film 36. After that, a contact hole 37 is formed in a portion of the interlayer insulating film 36 corresponding to the drain region 30c. Then, as shown in FIG. 3G, for example, by the PVD method,
A conductive material such as Al-Si is deposited on the interlayer insulating film 36, and the bit line 38 is formed through the contact hole 37.
(BL) is brought into contact with the drain region 30c. After that, although not shown, the entire surface is covered with a passivation film.

In the following description, the non-volatile memory element will be referred to as "memory transistor". FIG. 4 is an equivalent circuit diagram showing the electrical configuration of the nonvolatile memory device.
The electrical configuration of the nonvolatile memory device will be described with reference to FIG. As shown in FIG. 4, this nonvolatile memory device includes memory transistors 20A, 20B, 2 having offset gate floating gates FG shown in FIG. 1 and source electrodes SE extending to the offset regions.
Memory cells 21A, 21B consisting of 0C and 20D,
21C and 21D are arranged in a matrix along the row direction X and the column direction Y.

Memory transistors 20A, 20 in the memory cells 21A, 21B arranged along the row direction X
The word line WL1 is connected to the B control gate. The memory cell 21C along a row direction X are array, the memory transistors 20 in 21D
The word line WL is connected to the control gates of C and 20D.
2 are connected.

The memory transistors 20A, 20 in the memory cells 21A, 21C arranged along the column direction Y
The bit line BL1 is connected to the drain of C. Memory cells 21 arranged along the column direction Y
The bit line BL2 is connected to the drains of the memory transistors 20B and 20D in B and 21D. A source line S is commonly connected to the source electrode SE of the memory transistors 20A, 20B, 20C, and 20D in each memory cell 21A, 21B, 21C, and 21D, and a substrate line SUB is commonly connected to the substrate.

A row decoder LD is connected to the word lines WL1 and WL2. The row decoder LD applies a predetermined voltage to the word lines WL1 and WL2 when writing, erasing and reading information .

A column decoder CD is connected to the bit lines BL1 and BL2. Column decoder CD
Applies a predetermined voltage to the bit lines BL1 and BL2 when writing, erasing and reading information. This column decoder CD is used to read information
Sense amplifier S for detecting a change in the potential of the bit line
A is connected. In the figure, R1 and R2 are resistors.
It The source line S has a source control circuit SC
Are connected. The source control circuit SC applies a predetermined voltage to the source line S when writing, erasing and reading information.

A substrate control circuit SUBC is connected to the substrate line SUB. The substrate control circuit SUBC applies a predetermined voltage to the substrate line SUB when writing, erasing and reading information. The application operation of each predetermined voltage of the row decoder LD, the column decoder CD, the source control circuit SC, and the substrate control circuit SUBC will be described later.

Referring to Table 1 and FIGS. 5 to 7,
Each operation of writing, reading, and erasing information in the nonvolatile memory device will be described.

[0035]

[Table 1]

<Writing> FIG. 5 is an equivalent circuit diagram of the nonvolatile memory device at the time of writing. For example, the memory cell 21
It is assumed that information is written to A. First, the source control circuit SC (see FIG. 4) applies 0 V to the source line S, and the substrate control circuit SUBC (see FIG. 4) applies 0 V to the substrate line SUB. The row decoder LD (see FIG. 4) applies 10 V to the word line WL1 to which the selected memory cell 21A is connected to select the memory cell 21A. Therefore, the column decoder CD (see FIG. 4) selects the selected memory. 0V is applied to the bit line BL1 to which the cell 21A is connected. The row decoder applies 0V to the word line WL2 to which the non-selected memory cells 21C and 21D are connected, and the column decoder applies non-selected memory cells 21B and 21B.
7 for the bit line BL2 to which 21D is connected
Apply V.

Then, in the selected memory cell 21A, the substrate- float of the memory transistor 20A is selected.
Ingu FN tunneling current is generated between the gate, electrons by the FN tunnel current is injected into the floating gate FG. As a result, the selected memory cell 21A is in the information writing state. On the other hand, the non-selected memory cell 21
In B, 21C and 21D, no FN tunnel current is generated between the substrate and floating gate of the memory transistors 20B, 20C and 20D, and electrons are not injected into the floating gate FG. As a result, no information is written in the non-selected memory cells 21B, 21C, 21D.

The gate voltage required for conducting between the source and drain differs between the state where electrons are accumulated in the floating gate and the state where electrons are not accumulated. That is, the threshold voltage V _TH for conducting between the source and the drain has a high threshold V1 (for example, 7 V) when electrons are injected into the floating gate, and a low threshold when electrons are not injected. It takes a value V2 (for example, 1V). In this way, by setting the threshold voltage V _TH to two types, binary data of “1” or “0” can be stored in the memory cell. <Erase> FIG. 6 is an equivalent circuit diagram of the nonvolatile memory at the time of erasing. Information is erased collectively. First, the column decoder and the source control circuit open all bit lines BL1 and BL2 and the source line S.
In the (open) state, 10 V is applied to the substrate line SUB by the substrate control circuit, and 0 is applied to all the word lines WL1 and WL2 by the row decoder.
Apply V.

Then, all the memory cells 21A, 21A
Memory transistors 20A, 2 in B, 21C, 21D
A bias reverse to that at the time of writing information is applied between the 0B, 20C, and 20D substrate- control gates, and the electrons accumulated in the floating gate FG escape to the substrate side by the FN tunnel current. As a result, the information stored in all the memory cells 21A, 21B, 21C, 21D is erased at once.

Information may be erased by dividing it for each word line. That is, all bit lines BL
1, BL2 and the source line S are opened, and 10V is applied to the substrate line SUB so that 0V is applied to the word line WL1 to which the memory cells 21A and 21B for erasing information are connected. Apply,
If 10V is applied to the word line WL2 to which the unselected memory cells 21C and 21D are connected, the memory cells 21A and 21A arranged along the word line WL1
The information stored in 21B is erased. <Reading> FIG. 7 is an equivalent circuit diagram of the nonvolatile memory at the time of reading. For example, assume that the information stored in the memory cell 21A is read. First, the source control circuit applies 2V to the source line S, and the substrate control circuit applies 0V to the substrate line SUB.
Is applied. The word line WL1 to which the memory cell 21A to be read is connected by the row decoder
Is applied to the bit line BL1 to which the selected memory cell 21A is connected by the column decoder in order to select the memory cell 21A by applying the sense voltage 5V.
Apply V. On the other hand, by the row decoder, the word line W to which the non-selected memory cells 21C and 21D are connected
0V is applied to L2, and the column decoder opens the bit line BL2 to which the non-selected memory cells 21B and 21D are connected.

Then, if information has been written in the selected memory cell 21A, that memory transistor 20A
There is no conduction between the source and drain, and no channel is formed. That is, no cell current flows in the selected memory cell 21A. On the other hand, when the selected memory cell 21A is in the erased state of information, the source-drain of the memory transistor 20A becomes conductive and a channel is formed. That is, a cell current flows in the selected memory cell 21A. If this state is sensed by the decoders CD and LD and the sense amplifier SA (see FIG. 4), the selected memory cell 21
The information stored in A and 21B can be read.

Further, the reading of information may be performed collectively. That is, 2V is applied to the source line S, 0V is applied to all the bit lines BL1 and BL2 and the substrate line SUB, and a sense voltage of 5V is applied to all the word lines WL1 and WL2. Then, all the memory cells 21A, 21B, 21
The information stored in C and 21D is collectively read.

Alternatively, the reading may be performed by dividing each word line. That is, by applying a 2V to the source line S, along with previously applied to 0V with respect to all the bit lines BL1, BL2 and the substrate line SUB, applying a sense voltage 5V relative word <br/> Dorain WL1 Then, the information stored in the memory cells 21A and 21B arranged along the word line WL1 is read.

Here, the sense voltage is an intermediate voltage between V1 and V2, which are two kinds of values of the threshold voltage V _TH . Therefore, when this sense voltage is applied, conduction / non-conduction between the source and drain is determined by whether or not electrons are accumulated in the floating gate.
As described above, since the FN tunnel current is generated between the substrate and the floating gate and the information is rewritten by the FN tunnel current, the deterioration of the tunnel oxide film can be prevented and the number of rewritable times can be increased. , The information can be rewritten instantly.

In the following description, the memory transistors 20A, 20B, 20C and 20D are collectively referred to as "memory transistor 20". FIG. 8 is a diagram showing the operating principle of the memory transistor at the time of writing, and FIG. 9 is a diagram showing the operating principle of the memory transistor at the time of reading. The operation principle of the memory transistor will be described with reference to FIGS. 8 and 9. <Write> For example, as shown in FIG.
Suppose information is written to A. At this time, FIG. 8 (a)
As shown in (b) and (c), the memory transistor 20A in the selected memrist 21A and the unselected memory cell 21
Each floating gate 32 of the memory transistor 20C in C and the memory transistor 20B in the non-selected memory cell 21B is arranged with a predetermined offset distance from the source region 30b, and each floating gate 32 of each memory transistor 20A, 20B, 20C is Source region 30b is 0V
Is applied, the channel region between the floating gate 32 and the source region 30b is always the offset region OS.

At this time, in the selected memory cell 21A, as shown in FIG.
10V is applied to the control gate 34 of A, 0V is applied to the substrate 30, and 0 is applied to the drain region 30c.
Since V is applied, F is applied between the substrate 30 and the gate 34.
An N tunnel current is generated, and the FN tunnel current causes electrons to tunnel through the tunnel oxide film 31 and be injected into the floating gate 32.

Further, in the non-selected memory cell 21C sharing the bit line BL1 with the selected memory cell 21A, as shown in FIG.
Since 0V is applied to the 0C control gate 34, the drain region 30c, and the substrate 30, the memory transistor 20C does not operate. Therefore, the drain disturb does not occur in the non-selected memory cell 21C. That is, when the information is written in the memory cell 21C, the electrons accumulated in the floating gate 32 of the memory transistor 20C are not extracted to the drain region 30c, and the written information is not destroyed.

Further, in the non-selected memory cell 21B sharing the word line WL1 with the selected memory cell 21A, 10V is applied to the control gate 34 of the memory transistor 20B as shown in FIG. 8C. Since 0 V is applied to the substrate 30, the substrate 3
Although a potential difference is generated between the 0-gate 34, since 7 V is applied to the drain region 30c, the depletion layer 50 at the PN junction of the drain region 30c spreads to the boundary of the offset region OS, and this depletion occurs. Layer 50
Shuts off the FN tunnel current. Therefore, electrons are generated in the floating gate 32 by the FN tunnel current.
Since it is not injected into the gate, no gate disturb occurs. <Read> At the time of reading information, the information shown in FIGS.
0V is applied to the drain region 30c and the substrate 30 of the memory transistor 20 in the selected memory cell, and 2V is applied to the source region 30b.
Since the sense voltage 5V is applied to the control gate 34, the surface of the substrate 30 in the offset region OS is inverted, and the inversion layer 52 is generated.

At this time, as shown in FIG. 9A, if the electrons are accumulated in the floating gate 32 and the information is in a written state, the influence of the positive charge of the control gate 34 is accumulated in the floating gate 32. The electrons are blocked by the generated electrons and do not reach the surface of the substrate 30 directly below the floating gate 32. for that reason,
There is no conduction between the source region 30b and the drain region 30c,
No channel is formed. That is, no current flows through the memory transistor 20.

On the other hand, as shown in FIG. 9B, if the floating gate 32 is in the erased state of information in which electrons are not accumulated, the positive charge of the control gate 34 influences the substrate 30 immediately below the floating gate 32. Spans the surface. Then, electrons having a concentration equal to the hole concentration of the substrate 30 are induced on the surface of the substrate 30 to cause inversion. The electrons induced by this inversion connect with the inversion layer 52 in the offset region OS. As a result, conduction is established between the source region 30b and the drain region 30c, and the channel CH is formed. That is, a current flows through the memory transistor 20.

Since the information is read by utilizing the inversion of the offset area as described above, the read speed is as high as that of the flash memory. According to this embodiment, the substrate - between the floating gate by generating an FN tunnel current Upon writing information, not the memory transistors in the unselected memory cells sharing the selected memory cell and the bit line operate. In the non-selected memory cell that shares the word line with the selected memory cell, a potential difference occurs between the substrate and the control gate of the memory transistor, but the drain region PN
The depletion layer at the junction extends to the boundary of the offset region and F
Electrons are not injected into the floating gate because it blocks the N tunneling current. Therefore, the write disturb of the non-selected memory cell at the time of writing can be prevented.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, an example using a P-type silicon substrate is described, but an N-type silicon substrate is used to form a memory transistor.
It may be a P- channel type.

[0053]

As is apparent from the above description, according to the present invention, the number of rewritable times can be increased, information can be rewritten instantaneously, and write disturb at the time of writing information can be prevented.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the configuration of a nonvolatile memory element according to an example of the present invention.

FIG. 2 is a schematic cross-sectional view showing a method of manufacturing a nonvolatile memory element in the order of steps.

FIG. 3 is a schematic cross-sectional view showing the manufacturing method following the process of FIG. 2 in the order of steps.

FIG. 4 is an equivalent circuit diagram showing an electrical configuration of the nonvolatile memory device.

FIG. 5 is an equivalent circuit diagram of the nonvolatile memory device at the time of writing.

FIG. 6 is an equivalent circuit diagram of the nonvolatile memory device at the time of erasing.

FIG. 7 is an equivalent circuit diagram of the nonvolatile memory device at the time of reading.

FIG. 8 is a diagram showing an operation principle of a nonvolatile memory element at the time of writing.

FIG. 9 is a diagram showing an operating principle of a nonvolatile memory element at the time of reading.

FIG. 10 is an equivalent circuit diagram showing an electrical configuration of a conventional nonvolatile memory device.

FIG. 11 is a schematic cross-sectional view showing a configuration of a conventional nonvolatile memory element.

FIG. 12 is a diagram showing a drain disturb at the time of writing.

FIG. 13 is a diagram showing a gate disturb at the time of writing.

[Explanation of symbols]

20, 20A, 20B, 20C, 20D Nonvolatile storage element (memory transistor) 21A, 21B, 21C, 21D Memory cell 30a Channel region 30b Source region 30c Drain region 30 Silicon substrate 31 Tunnel oxide film 32, FG Floating gate 33 ONO Film (capacitor insulating film) 34 Control gate 40, SE Source electrode D Offset interval WL1, WL2 Word line BL1, BL2 Bit line S Source line SUB Substrate line LD Row decoder CD Column decoder SA Sense amplifier SC Source control circuit SUBC Substrate control circuit

Front page continued (72) Inventor Takanori Ozawa 21 ROHM Co., Ltd., Mizozaki-cho, Saiin, Ukyo-ku, Kyoto (56) References JP-A-6-314795 (JP, A) JP-A-4-91471 (JP, A) Special Kaihei 3-112166 (JP, A) JP-A-4-229655 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/788 H01L 29/792 H01L 27/115 H01L 21/8247

Claims (3)

(57) [Claims] 1. A or injecting charge, there is performed the storage of information by taking out, opened and the semiconductor substrate, a predetermined distance in the surface layer of the semiconductor substrate with a predetermined Ru conductivity type The source region and the drain region formed by the above and the channel region formed so as to be sandwiched between the source region and the drain region are formed with a predetermined offset distance from the source region to tunnel the charges generated in the channel region. A tunnel insulating film to be obtained, a floating gate formed on the tunnel insulating film for accumulating charges tunneled through the tunnel insulating film, a capacitor insulating film formed on the floating gate for confining charges in the floating gate, Control that is formed on the capacitor insulating film and that is applied with a predetermined control voltage And over bets, along with in contact with the source region, read out information
When a read voltage is applied at
The offset, which is the channel region between the tunnel insulating film and
A floating gate, a capacitor insulating film, and a source electrode that are insulated from the control gate and extend over the offset region through the insulating film so that the gate region can be inverted. A non-volatile memory element characterized by the above. 2. A nonvolatile memory element according to claim 1, wherein the nonvolatile memory element is formed in a matrix on a semiconductor substrate along a row direction and a column direction, and is arranged along the row direction. A word line is connected to the control gate, a bit line is connected to the drain region of the nonvolatile memory elements arranged along the column direction, and a source line is connected to the source electrode of each nonvolatile memory element. A non-volatile memory device, which is commonly connected and has a common substrate line provided on the semiconductor substrates. 3. A method for driving a non-volatile memory device according to claim 2, wherein a source line and a substrate line are set to a ground potential when writing information, and a non-volatile memory element for writing is connected. Half of the ground potential for the word line
FN tunnel between conductor substrate and floating gate
It applies a high voltage can cause a current, it than
In order to select the non-volatile memory element for writing with the external word line at the ground potential , the write voltage is applied to the bit line connected to the non-volatile memory element and to the other bit lines. Write-protected
By applying a voltage, an FN tunnel current is generated between the substrate and the floating gate of the selected nonvolatile memory element, and the FN tunnel current injects charges into the floating gate. and leave the source line and open state, the word line non-volatile memory device for erasing the information is connected to the ground potential,
Semiconductor substrate and floating gate for substrate line
A high voltage that can generate an FN tunnel current is applied between
To the substrate of the selected nonvolatile memory element - Floating
It generates an FN tunnel current in the direction opposite to that in the writing between ring gate, the charge accumulated in the floating gate escape to the substrate side, when reading information, the board line and the ground potential by the FN tunnel current, source A non-volatile memory that performs a read by applying a read voltage that can invert the substrate surface in the offset region to the line and a sense voltage to the word line to which the non-volatile memory element that performs the read is connected A method for driving a non-volatile memory device, comprising setting a bit line connected to the non-volatile memory element to a ground potential to select the element.