JPS6223173A - Mos type nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To form a gate insulating layer including a charge trapping center only by using one oxidizing device by shaping a first SiO2 layer formed onto the surface of an Si substrate, a second SiO2 layer containing a large quantity of Si clusters shaped onto the first SiO2 layer and a gate electrode formed onto the second SiO2 layer. CONSTITUTION:An Si substrate 1 is mounted into an oxidizing device, an SiO2 layer 3 containing a large quantity of Si clusters 11 is shaped through oxidation at low-temperature high steam pressure first, an oxidizing atmosphere at high steam pressure is purged by an inert gas, and an SiO2 layer 2 containing no Si cluster is formed on the interface between the SiO2 layer 3 and the Si substrate 1 previously shaped through a temperature rise and second oxidation at high-temperature low steam pressure. The Si clusters 11 in the SiO2 layer 3 are also oxidized on the formation of the SiO2 layer 2, but the Si clusters are not annihilated even when some shrinkage of the size of the Si clusters 11 or some reduction in numbers is generated so far as the thickness of the SiO2 layer 2 is extremely thin as 15-30Angstrom .

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type nonvolatile semiconductor memory device, and particularly to the structure of a gate insulating layer.

[Conventional technology]

A MOS type nonvolatile semiconductor memory device utilizes a change in threshold voltage caused by charges captured at a charge trapping center existing in a gate insulating field. Therefore, a MOS type nonvolatile semiconductor memory device is characterized by the structure of the gate insulating layer.

Gate insulating layers of conventional MOS type nonvolatile semiconductor memory devices have the following two types of structures.

The first is MNO8 (Metal -N1tride -0
The second is a gate insulating layer having a double dielectric structure represented by xide-5i-1icon), and the second is a floating gate structure.

As shown in FIG. 3 (al), the gate insulating layer of the double dielectric structure has a thickness of 15 to 30 nm as the first dielectric layer on the surface of the Si substrate 1.
A tD SiO2 layer 31 with a thickness of 450 mm is formed as a second dielectric layer on the surface of the first dielectric layer.
An amorphous Si3N4 layer 32 of ~800 nm thick is formed. Further, a gate insulating layer 33 made of a polycrystalline Si layer is formed on the surface of the second dielectric layer.

In this structure, 1-1. The loading center is amorphous 5iaN
Charges existing in the a layer 32 and captured by Xl are directly injected from the surface of the Si substrate 1 through the Si0g layer 31 into the amorphous Si3N4 layer 32 by a tunneling effect.

As shown in FIG.
A SiO2 layer 41 with a thickness of ˜200 μm is formed, and an additional 300 μm thick SiO2 layer 41 is formed on the surface of the first dielectric layer.

A polycrystalline Si skin 42 with a human thickness is formed.

Further, on the surface of the polycrystalline Si layer 42, a Si02 layer 43 having a thickness of 1000 to 5000 layers is formed as a second dielectric layer, and furthermore, a gate electrode 44 made of polycrystalline 5iNI is formed on the surface of the second dielectric layer. is formed. In this structure, the charge trapping center is in the polycrystalline StI layer 42, and the compensated charge is generated at high energy by avalanche breakdown of the p-n junction composed of the drain (not shown) and the Si substrate 1. It is excited and injected into the polycrystalline Si layer 42 through the first SiO layer 41.

In either structure, the Si substrate 1 and the amorphous Si3N4 layer 32 or polycrystalline Si layer 42, which contains the entire charge trapping center, are separated by 5i027 so 31 or 41, which acts as a barrier to the free movement of charges. What they have in common is that they have a structure.

[Problem that the invention seeks to solve]

As is clear from its structure, the gate insulating layer of the conventional MOS type nonvolatile semiconductor device described above has a stacked structure of different materials. For this purpose, a plurality of devices must be sequentially used to form the gate insulating layer.

For example, to form a gate insulating layer with a double dielectric configuration, a Si substrate 1 is first thermally oxidized in an oxidizer to
0A thick SiO/131', then LPC
Amorphous 5izN with a thickness of 450-800 in vD equipment
Four layers 32 are formed.

However, to form the gate insulating layer of the floating gate structure,
First, a Si substrate 1 is thermally oxidized in an oxidizer to give a
Form a first SiO layer 41 with a thickness of
Polycrystalline S with a thickness of 2000-5000 in CvD equipment
The i-layer 42 is formed and then thermally oxidized again in an oxidizer to form a second SiO layer 43 with a thickness of 5,000 to 5,000 nm. The second 8iOz layer 43 is polycrystalline Si/142t
- Since it is obtained by oxidation, the thickness of the polycrystalline S i /It 42 is 300 to 1000 as a result of the 20th thermal oxidation.

Furthermore, in the floating gate structure, the polycrystalline Si layer 42 must be selectively formed within the gate insulating layer;
A step of selectively removing the polycrystalline Si layer 42 is required between the step of forming the polycrystalline Si layer 42 using the PCVD apparatus and the 20th thermal oxidation step.

As described above, the conventional MOS type nonvolatile semiconductor device has the disadvantage that the gate insulating layer is formed using a plurality of devices and through a plurality of steps.

An object of the present invention is to eliminate the complexity of the gate insulating layer forming process of the conventional MO3 type nonvolatile semiconductor device, and to form a gate insulating layer containing a charge trapping center using only one oxidation device. M with a gate insulating layer of possible novel structure
An object of the present invention is to provide an OS type nonvolatile semiconductor memory device.

[Means for solving problems]

The MOS type nonvolatile semiconductor memory device of the first invention includes S
A first SiO layer formed on the surface of the i-substrate, a second SiOz layer formed on this first SiO2 layer and containing a large amount of tSi clusters, and a second SiOz layer formed on this second SiO2 layer. The gate electrode is configured to include a gate electrode.

The MOS type non-volatile semiconductor memory device of the second invention includes S
A first SiOz layer formed on the surface of the i-substrate, a second SiO layer formed on the first SiO2 layer containing a large amount of tSi clusters, and a second SiO2 layer formed on the second SiO2 layer. The structure includes three SiO layers and a t-gate electrode formed on the third SiO layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

In the thermal oxidation of a Si substrate, (11 oxidation is 5
This is a chemical reaction that occurs at the i-8iOz interface, and therefore oxidation progresses toward the Si side of the 5i-8iOz interface.

(2) The structure of the SiO layer formed differs depending on the oxidation conditions (temperature, water vapor partial pressure, etc.). There are a large number of S1 clusters.

This is based on the experimental fact that.

FIG. 1 is a longitudinal sectional view of a first embodiment of the invention.

In FIG. 1, a first 8io2 layer 2 with a thickness of 15 to 30 layers is formed on the surface of a Si substrate 1, and a first 5iC layer 2 is formed on the surface of a Si substrate 1.
) + thickness 4 containing a large amount of Si clusters 11 on the surface of layer 2
A second SiO2 layer 3 of 50-800 layers is formed. Further, a polycrystalline St layer is formed as a gate electrode 5 on the sixth layer of the second Si02 layer 3.

In this example, the first SiO2 layer 2 acts as a barrier to free movement of charges, and the SiO2 layer 3 in the second SiO2 layer 3 acts as a barrier to free movement of charges.
Cluster 11 serves as a charge center.

In the structure of this embodiment, a Si substrate 1 is installed in an oxidation device,
First, by oxidizing at low temperature and high water vapor pressure, a Si cluster 1lt-SiO layer 3 containing a large amount is formed. After that, the oxidizing atmosphere with high water vapor pressure is purged with an inert gas, and the temperature is raised to under high temperature and low water vapor pressure. This can be obtained by oxidizing the Si0g layer 2 containing no Si clusters at the interface between the SiO2 layer 3 and the Si substrate 1, which have already been formed. When forming the SiO layer 2, Si
Although the Si clusters 11 in the oz layer 3 are also oxidized, SiO
As long as the thickness of layer 2 is thin, such as 15 to 30 people, the Si clusters will not disappear even if the size of the Si clusters it or the number of them decreases slightly. do not have.

FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.

In this embodiment, as shown in FIG. 2, a Si
A third 8 i Oz layer 4 without clusters is formed. According to the structure of this embodiment, the charges trapped in the Si clusters 11 in the second SiO layer 3 move to the gate electrode 5 side by hopping conduction, and further, the charges are transferred to the gate electrode 5 side.
Since the third SiO layer 4 can prevent the release of hydrogen into the air, nonvolatility, which is the main point of a nonvolatile memory device, can be further strengthened.

The structure of this second embodiment is similar to that of the first embodiment.
The i-substrate I is placed in an oxidation apparatus, and after forming an 8I0z layer 4 containing no Si clusters at high temperature and low water vapor pressure, the oxidizing atmosphere at low water vapor pressure is purged and the temperature is lowered. Thereafter, the SiOz layer 3 containing a large amount of Si clusters lit'' and the SiO layer 2 having a thickness of 15 to 30 Å are sequentially formed in accordance with the same procedure as in the first embodiment.

〔Effect of the invention〕

As explained above, in the MOS type nonvolatile semiconductor memory device of the present invention, since the gate insulating layer has a layered structure of essentially homogeneous materials, it can be formed continuously in one oxidation device. . In comparison, unlike the gate insulating layer in a conventional MOS type nonvolatile semiconductor memory device, the process for forming the gate insulating layer can be simplified.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of a first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a second embodiment of the present invention, and FIG.
bl is a vertical cross-sectional view of a gate insulating layer of a conventional MOS type nonvolatile semiconductor memory device. 1゛°・・・Si substrate, 2.4.31・・・S
iO layer, 3... Sing layer s 5 , 3s containing Si clusters. 44... Gate electrode, 11... Si cluster, 32... Si 3N4 layer, 42...
...Polycrystalline Si layer.゛、′ V3 times

Claims (2)

[Claims] (1) A first SiO_2 layer formed on the surface of the Si substrate, a second SiO_2 layer containing a large amount of Si clusters formed on the first SiO_2 layer, and a second SiO_2 layer formed on the second SiO_2 layer. A MO characterized by comprising a gate electrode.
S-type nonvolatile semiconductor memory device. (2) A first SiO_2 layer formed on the surface of the Si substrate, a second SiO_2 layer containing a large amount of Si clusters formed on the first SiO_2 layer, and a second SiO_2 layer formed on the second SiO layer. a third SiO_2 layer; and a third SiO_2 layer.
1. A MOS type nonvolatile semiconductor memory device, comprising: a gate electrode formed on the layer.