JPH04137564A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the level of integration by providing a region in which conductive silicon and insulative silicon dioxide mixedly exist between the channel region and the control gate of an MOS transistor for storage. CONSTITUTION:The whole of a storage hold part 6 is formed of insulative silicon dioxide. In the inside, conductive silicon mixedly exists in the form of points. The silicon maintains a state of complete dielectric isolation at a voltage of an ordinary operation level. When a comparatively high voltage is applied to a control gate or a channel, electrons are injected and erased by tunnel effect. In this case, a part corresponding to a floating gate formed by a conventional technique is divided into very small regions, whose peripheral parts are surround by insulative films 8. Hence, even when a few defects exist in the insulative films and short-circuit is generated, the function is not affected as a whole, so that the level of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to an EPROM that is widely used in electronic equipment as a nonvolatile semiconductor memory device.

B. Prior Art There are two types of conventional EPROMs, MNOS type and floating gate type, depending on the structure of the storage MOS transistor.

In the former, a thin film of silicon dioxide/phosphoric acid and a silicon nitride thin film are laminated on the channel region of a storage MOS transistor, and a control gate is placed on top of this, and information is stored by sending electrons to the trap level existing in the silicon nitride thin film. This is done by injection.

In the latter, a floating gate made of polycrystalline silicon insulated from the surroundings is provided in a silicon dioxide thin film laminated on the channel region, and information is stored by injecting electrons into this floating gate.

Problems to be Solved by the Invention In the conventional EPROM described above, the MNOS type has a relatively low density of trap levels in silicon nitride, and the injected electrons move to some extent in the silicon nitride thin film. However, since the thickness of the silicon nitride thin film cannot be made very thin, the shape of the MOS transistor inevitably becomes thick (which becomes an obstacle to increasing the degree of integration).

In the floating gate type, if there is even one defect in the silicon dioxide thin film surrounding the floating gate, the entire transistor becomes inoperable, so the thickness of the silicon dioxide thin film cannot be made very thin, which also makes it difficult to increase the degree of integration. This had become an obstacle.

means to solve the problem This invention was made based on the above circumstances.

In this invention, a region where conductive silicon and insulating silicon dioxide are mixed is provided between the channel region and the control gate of a memory MOS transistor, and information is stored in this region. .

Function As described above, in the present invention, a region of conductive silicon and insulating silicon dioxide is provided between the channel region and the control gate of the storage MOS transistor.

Here, the conductive silicon is in the form of small particles and is independent of each other.

The thickness of the insulating silicon dioxide surrounding the conductive layer is controlled to such a level that no electron injection or erasure occurs at normal operating levels, but at relatively high voltages the above phenomenon occurs.

Therefore, although information can be easily stored or erased by applying a relatively high voltage, the storage will not be erased under normal operation.

F Example Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a storage MO of a semiconductor storage device according to the present invention.
FIG. 3 is a partial cross-sectional view of an S transistor.

In the figure, 1 is a semiconductor substrate.

If the memory MOS transistor is of P channel type, this semiconductor substrate is of N type.

Reference numerals 2 and 3 denote source and drain regions, both of which are formed by P-type impurity amended regions.

Reference numerals 3 and 4 are source and drain electrodes, respectively, which are usually made of metal such as aluminum.

8 is an insulating film deposited to cover the entire surface of the semiconductor substrate.

Reference numeral 7 denotes a control gate electrode, which is usually made of aluminum or polycrystalline silicon.

Reference numeral 6 denotes a memory storage part according to the present invention, which is entirely made of insulating silicon dioxide, but has conductive /
Recon is mixed in dots.

The conductive silicon dots remain completely isolated at normal operating voltage levels.

However, when a relatively high voltage is applied to the control gate or channel, electrons are injected and erased due to the tunneling effect.

This storage portion can be easily formed by using, for example, a sputter deposition technique and using a mixture of silicon and silicon dioxide as a target.

It can also be formed by using chemical vapor deposition technology and appropriately adjusting the atmospheric gas.

In this example, the case where the memory storage part is in direct contact with the channel or the control gate electrode has been explained, but in order to improve the yield rate and reliability, a thin insulating coating is applied to the surface of the channel region or directly under the control gate electrode. It works in exactly the same way even if you put it on.

It goes without saying that various other modifications can be made without departing from the gist of the invention.

G. Effects of the Invention As described above in detail, according to the present invention, the portion corresponding to the floating gate in the prior art is separated into extremely small regions and surrounded by an insulating film.

Therefore, even if there is a slight defect in the insulating film and a short circuit occurs, the overall function is hardly affected.

Therefore, since the thickness of the insulating film can be made sufficiently thin, it can greatly contribute to improving the performance and degree of integration of semiconductor memory devices.

[Brief explanation of the drawing]

FIG. 1 shows a storage MO of a semiconductor storage device according to the present invention.
FIG. 3 is a partial cross-sectional view of an S transistor. l... Semiconductor substrate 2... Source region 3... Source electrode 4... Drain region 5... ...Drain 11 pole 6...Memory holding part 7...Control gate electrode 8...
...Insulating film

Claims (1)

[Claims] A semiconductor memory device characterized in that a MOS transistor used for storing information has a region above a channel region and below a control gate electrode in which conductive silicon and insulating silicon dioxide coexist.