JPS61127177A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device using two or more non-single crystal semiconductor layers and a method for manufacturing the same.

[Technical background of the invention and its problems]

As a semiconductor device using a non-single crystal semiconductor 1- of 2 II or higher, I3p OM and lit! FROM, DRAM, etc. are known.

In gP, FLOM, 71:i-ting gate band'
The information content is determined by the magnitude of the current flowing through channels formed on opposing semiconductor surfaces depending on the solder state. Because the insulating film is thick, avalanche breakdown of the drain junction occurs on the semiconductor substrate surface, and the high-energy carriers generated there cross the barrier between the insulating film and the semiconductor surface and are injected into the floating gate, where information is written. This is done by exciting and expelling carriers from the floating gate by irradiating the floating gate with ultraviolet rays, X-rays, etc.

In Fi''FROM, reading and writing are performed by determining that the threshold voltage seen from the control gate provided through the insulator 1 on the floating gate differs depending on the IT state of the floating gate. , 70− by tunneling or avalanche injection of carriers of opposite sign.
This is done by injecting it into the charging gate and neutralizing the charge.

Here, an EFROM will be described as a specific example.

FIG. 3 is a sectional view of a conventional FiPPOM, and FIG. 4 is a sectional view of its manufacturing process.

As shown in FIG. 3, a conventional gPROM has a single crystal silicon substrate 31. First, the first silicon oxide film 32, the first polycrystalline silicon 1-33, the second polycrystalline silicon oxide film 34, and the second polycrystalline silicon 1-35 are sequentially laminated. It is being The first polycrystalline silicon layer 33 functions as a floating gate, and the second polycrystalline silicon layer 35 functions as a control gate.

The manufacturing process is shown in FIG. As shown in FIG. 4(,), a first silicon oxide film 32 is formed on a single crystal silicon substrate 31, and a first polycrystalline silicon layer 33 is formed on the upper surface of the first silicon oxide film 32.
is formed, and impurity diffusion or ion implantation is performed as necessary.

Next, as shown in FIG. 4(b), a second silicon oxide film 34 is formed, and a second polycrystalline silicon layer 35 is formed on its upper surface.
form. Next, as shown in FIG. 4(C), the second polycrystalline silicon layer 35, the second silicon oxide film 34, and the first
polycrystalline silicon layer 33 and first silicon oxide plX3
2t-patterning. Furthermore, using the patterned second polycrystalline silicon layer 35 as a mask, impurity ions are implanted to form source/drain regions 37. Next, as shown in FIG. 4(d), a third silicon oxide film 36 is formed.

When forming the second silicon oxide film 34t, the first polycrystalline silicon layer 33 in which phosphorus has been diffused has a large oxidation temperature. The formation is pyramidal. However, in general, the surface of polycrystalline silicon is not a smooth plane like the one-sided surface of single-crystal silicon, but is extremely uneven, so oxidation at low temperatures will make the unevenness more severe, making it difficult to use in actual use. In this case, since the direct rising concentration occurs at the tip of the convex state, the leakage withstand voltage becomes large, and the dielectric withstand voltage becomes small. When comparing the withstand voltage of polycrystalline silicon oxide film and single crystal silicon oxide film using 100 samples each, the former has a dielectric strength of about 3 CMV/m as shown in Figure 5).
It is known that the latter has a high IQ (MY/z) as shown in Figure 5BK.Also, polycrystalline silicon oxide film C has a higher pinhole density than single crystal silicon oxide film. It is also known that the insulation properties are poor. Therefore, in the conventional example shown in FIG. 3, since the insulating film between the high-voltage, thin-film, and single-layer polycrystalline silicon 1 is formed using an inner cone, the 70-ring gate and the control gate are The combination of appearance-e becomes more likely to rise. In this case, since the 70-digit gate cannot be made sufficiently high, there are restrictions on the writing amount, writing speed, etc.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device having an insulating structure capable of achieving excellent insulating properties and large capacitive coupling between two or more non-single crystal semiconductor layers, and a method for manufacturing the same.

[Summary of the invention]

In the present invention, metal oxide 1 is added to the first non-single crystal semiconductor layer.
Non-single crystal semiconductor 1-f of threat and $2: formed and said 31-
After patterning into a predetermined shape, heat treatment is performed in a wet oxygen atmosphere to form polyinterfaces between the first non-single crystal semiconductor layer, the metal oxide layer, the metal/fecal material 4, and the second non-single crystal semiconductor 119. A semiconductor device having an insulating structure obtained by forming an insulating film and a method for manufacturing the same.

[Embodiments of the invention]

8280M will be described as an embodiment of the present invention.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a nine gf'ROM according to the present invention, and FIG. 2 is a sectional view of its manufacturing process.

As shown in FIG. 1, in this embodiment, a silicon oxide film 12 is formed on a single crystal silicon substrate 11, and a first
polycrystalline silicon layer 13 and first silicon oxide film 14
It has a structure in which a tantalum oxide layer (Ta205) 15, a second silicon oxide film 16, a second polycrystalline silicon 1-17, and a $3 silicon/oxide film 18 are sequentially stacked. . The first polycrystalline silicon layer 13 acts as a floating gate, and the second polycrystalline silicon layer 1117 acts as a control gate.

As shown in FIG. 2, a silicon oxide film 12 is formed by thermal oxidation at 900° C. in a VC dry oxygen atmosphere on a single crystal silicon substrate 11, and then The first polycrystalline silicon 711!1 using the method
3 is formed to a thickness of 2000λ, and impurity diffusion or 1d ion implantation is performed as necessary. Next, as shown in FIG. 2(b), tantalum (T2) is formed to a thickness of 200λ using a sputtering method, and then a layer of tantalum (T2) is formed to a thickness of 400λ using a thermal oxidation method.
・Tantalum oxide (TazOs) 15 is oxidized from 3
00λ thickness and chemical vapor deposition CCV on the E side.
The second polycrystalline silicon using the D1 method) 17 to 200
It is formed to a thickness of 0λ, and impurity ions are implanted as necessary. Next, as shown in FIG. 2<c>, the second polycrystalline silicon layer 17, the tantalum oxide layer 15, and the first polycrystalline silicon layer 13 are etched into a predetermined shape using reactive ion etching (RIFtl). After patterning, impurity ions are implanted to form source/drain regions using the second polycrystalline silicon layer 17 as a mask.
As shown in Figure 117J2 (d), by performing heat treatment for 30 minutes in a wet oxygen atmosphere at 1000°C, the first polycrystalline silicon layer 13 and tantalum oxide! #1
At the same time, the interface between the first polycrystalline silicon+113 and tantalum oxide 1a15 and the second polycrystalline silicon layer 17 are oxidized.
A $1 silicon oxide film 14 and a second silicon oxide film 16 are formed on the M interface of the tantalum oxide layer 15. This is because the tantalum oxide layer 15 serves as an oxygen introduction path and supplies oxygen from the exposed portion of the tantalum oxide layer 150 to each interface.

Comparison of the 4 voltage resistance of the insulation structure between two layers of polycrystalline silicon 711 consisting of three layers of silicon oxide film, tantalum oxide, and silicon oxide film, and the one made of polycrystalline silicon oxide film using 100 samples each. In this case, the former is the sixth
As shown in the figure, it is about 13 [: MV/yR], and the latter is about 3 (MV/m) as shown in FIG. As described above, by implementing the present invention in the i113FROM, it is possible to increase the coupling capacitance between gates without deteriorating the insulation properties, even though the film thickness of each gate tends to become thinner as the size is reduced. . Therefore, the effect of increasing the writing speed and increasing the cutting age can be obtained.

Also, zirconium oxide (Zr02) can be used instead of tantalum oxide (Ta2es) as the metal oxide.

In addition, semiconductor devices having two or more layers of non-single crystal semiconductors such as 280M and D-AM are known, but the present invention naturally relates to semiconductor devices having two or more layers of non-single crystal semiconductors. The present invention is also applied to semiconductor devices and methods for manufacturing the same, which require high-voltage, large-capacity glabellar insulating films.

〔Effect of the invention〕

According to the present invention, in a semiconductor device having 21 or more non-single-crystal semiconductors, the performance of various semiconductor devices can be improved by providing a high breakdown voltage, thin film, and large capacity insulation structure as an insulating film between the semiconductors. You can use it as a guide.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention, Fig. 2 is a sectional view of the manufacturing process of Fig. 1, and Fig. 3 is a sectional view of a conventional example. Figure 4 is a cross-sectional view of the fabrication process of Figure 3, and Figure 5 is a graph showing the relationship between the withstand voltage and its ratio for the oxide film in a test using 100 samples. , k is for polycrystalline silicon and B is for single-crystalline silicon. Figure 6 is 10
This is a graph showing the relationship between the withstand voltage and its ratio for an insulating film between two layers of polycrystalline silicon in 9 tests using 0 samples, where C is a silicon oxide film. Dk-i silicon oxide film and tantalum oxide (Ta205
) and a silicon oxide film 3111. 11.31... monomarctic silicon substrate. 13, 33...first polycrystalline silicon layer. 14...Silicone c atomization film of fXl. 15...Tantalum oxide 11゜16...
-Second silicon oxide film. 17.35...Second polycrystalline silicon layer. 19, 37... Source/drain region. 'Representative Patent Attorney Noriyuki Chika (and 1 other person) Fig. 2 114 Fig. 5 Fig. 6 Dielectric strength CMV/cm 1

Claims (2)

[Claims] (1) In a semiconductor device in which a first non-single-crystal semiconductor layer and a second non-single-crystal semiconductor layer are stacked with an insulating film interposed therebetween, the first non-single-crystal semiconductor layer and the first non-single-crystal semiconductor layer A first insulating layer formed on the semiconductor layer, a metal oxide layer formed on the first insulating layer, and a second insulating layer formed on the metal oxide layer. , and a second non-single crystal semiconductor layer formed on the second insulating layer. (2) forming a metal oxide layer on the first non-single crystal semiconductor layer; forming a second non-single crystal semiconductor layer on the metal oxide layer; A step of patterning the crystalline semiconductor layer, the metal oxide, and the second non-single crystal semiconductor layer into a predetermined shape, and performing heat treatment in a wet oxygen atmosphere to form the first non-single crystal semiconductor layer and the metal oxide. A method for manufacturing a semiconductor device, comprising the step of forming an insulating layer at an interface between the second non-single crystal semiconductor layer and the metal oxide.