JPS6223168A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To design impurity concentration in both an impurity region for controlling threshold voltage and low-concentration impurity regions for source-drain independently and optimally by changing the depth of both regions. CONSTITUTION:An N channel MOS transistor is formed onto a P-type Si substrate 13, and high-concentration N-type impurity layers 14 and low- concentration N-type impurity layers 12 are used as source-drain diffusion layers. The concentration of the impurity layer 12 is brought to 10<16>-10<19>cm<-3>, and an impurity layer 15 consists of an impurity layer having the same P-type as the substrate, and concentration thereof is brought to 10<16>-10<19>cm<-3>. The superposing sections of the impurity layers 15 and the impurity layers 12 can be reduced extremely. Accordingly, both impurity distribution of the impurity layer for controlling threshold voltage and the low-concentration source-drain diffusion layer adjacent to a gate electrode can precisely by controlled independently, thus designing a MOS transistor having high reliability and high performance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a fine MoS transistor structure, and particularly to a transistor structure with higher reliability than conventional transistor structures.

[Background of the invention]

With the miniaturization of MoS transistors, transistor deterioration due to hot carriers has become a problem.

In order to deal with this, Fig. 2 (Japanese Unexamined Patent Publication No. 51-61117
76), a method of forming a low impurity concentration region 2 of the same conductivity type as the source/drain in the source/drain region adjacent to the gate electrode 1 to reduce the electric field near the drain and reduce the generation of hot carriers. is taken.

2 is an impurity layer having the same conductivity type as the semiconductor substrate 3 formed by implanting impurity ions for controlling the threshold voltage of a MOS transistor. In this structure, since the impurity layer 5 and the low concentration impurity layer 2 overlap, the impurity concentration of the impurity layer 2 is substantially reduced, resulting in an increase in resistance, which makes it difficult to achieve an optimal design.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems and provide a fine MOS transistor structure with high reliability and high performance.

(Summary of the Invention) In order to achieve the above object, the present invention reduces the impurity concentration of both impurity regions by changing the depths of the impurity region for threshold voltage control and the low concentration impurity regions of the source/drain. Optimum design is possible independently.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

The first embodiment shown in FIG. 1 is an n-channel MOS transistor formed on a p-type Si substrate 13, with a heavily doped n-type impurity layer 14. A low concentration n-type impurity layer 12 is used as a source/drain diffusion layer. The concentration of impurity layer 12 is 101@~101sl''3. Impurity layer 15
is the same p-type impurity layer as the substrate, and the concentration is l O”
~1-0 "aI+-".

Since this impurity layer 15 is located in a deeper region than the impurity layer 12, it is possible to reduce the overlapping portion between the impurity layer 15 and the impurity layer 12 as much as possible. Therefore, it is possible to optimally design and control the impurity concentration distribution in both impurity regions, and it is possible to achieve both high reliability and high performance of the transistor.

A second embodiment is shown in FIG. The figure shows an n-channel MOS transistor formed on a p-type Si substrate 23, with a high concentration n-type impurity layer 24. The low concentration n-type impurity layer 22 is used as a source/drain diffusion layer. The concentration of the impurity layer 22 is 101@ to 1019cn-'. Impurity layer 2
5 is the same p-type impurity layer as the substrate, and the concentration is 1016
~IQ"cm-'. Since this impurity layer 25 is in a shallower region than the impurity layer 22, it is possible to reduce the overlapping portion of both impurity layers as much as possible, and the concentration distribution of both impurity layers can be optimally designed and controlled. It is possible.

FIG. 4 shows the manufacturing process of the embodiment (see FIG. 1). Gate oxide film (e.g. 20 nm) on p-type Si substrate
After forming by thermal oxidation method, boron 33 is formed by ion implantation method (for example, implantation acceleration voltage 120 kV, dose amount 5
X 10”am-3) Te driving (Fig. 1a), Si
After forming a high concentration layer 35 of boron inside, a gate electrode 36 (for example, polycrystalline Si doped with phosphorus) is formed (FIG. 1b).

Next, phosphorus 37 was added by ion implantation method (for example, implantation acceleration voltage 30 KV, dose amount I X I O"am-")
A low concentration n-type impurity region 38 is formed in a self-mixing manner with respect to the gate electrode 36 (FIG. 1c), and then C.
VD (Chemical Vapor Deposition Chemi)
cal Vapor Deposition) method.

After depositing the Sin, 39 (FIG. 1d), the CvDSi02 is etched using an anisotropic dry etching method, leaving the Sin, 40 on the sidewalls of the gate electrode (FIG. 1e).

Next, ion implantation method (for example, implantation acceleration voltage 40
Arsenic 41 is implanted at a dose of 5 x 101 s-2 to form a highly concentrated n-type impurity layer 42 (see Fig. 1 f).
)0 or more, it is possible to realize a desired MOS transistor structure. Note that the structure shown in FIG. 3 can also be realized by lowering the ion implantation acceleration voltage of boron 33 to about 10 kV and increasing the implantation acceleration voltage of phosphorus 37 to about 200 kV or more.

In this embodiment, the present invention has been explained using an n-channel MOS transistor as an example, but it goes without saying that the effects of the present invention can be exhibited by applying the present invention to a p-channel MOS transistor. It is also possible to realize a complementary MO3 that combines an n-channel MOS transistor and a p-channel MOS transistor employing the structure according to the present invention.

〔Effect of the invention〕

By using the structure of the present invention, it becomes possible to independently and accurately control the impurity distribution of both the threshold voltage control impurity layer and the low concentration source/drain diffusion layer adjacent to the gate electrode. This has the effect of enabling high-performance MOS transistor design.

[Brief explanation of the drawing]

1 and 3 are cross-sectional views of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventionally structured MOS transistor, and FIG. 4 shows a manufacturing process of the MOS transistor of FIG. 2. 1.11, 21.36...gate electrode, 2,12°2
2.38...Low concentration source/drain diffusion layer, 3゜1
,． 3,23.31...P-type Si substrate, 4,14°2
4.42...High concentration source/drain diffusion layer, 5゜1
5.25, 34.35...p-type impurity W for threshold voltage adjustment, 6,16,26.32-...Goo 1-absolute a film, 3
3...Boron, 37...phosphorus, 39.40...C
VD5jO2,41...Arsenic. Agent: Patent attorney Katsuma Ogawa 71. ＼−−２〆次／Fig/l □亦ノ+7已1ノ】

Claims (1)

[Claims] 1. In a MIS transistor having a second conductivity type source/drain region formed in a first conductivity type region of a semiconductor substrate, a surface portion of the source/drain region of the transistor adjacent to the gate electrode. The first conductivity type of the semiconductor substrate is a region where the impurity concentration of A semiconductor device comprising a first conductivity type impurity region having a higher concentration than the impurity region. 2. Among the source/drain regions, the low concentration impurity region adjacent to the gate electrode is inside the substrate, and the low concentration impurity region is adjacent to the gate electrode.
A first conductivity type impurity region having a higher concentration than the first conductive electrode impurity region of the semiconductor substrate is provided in a region not deeper than the drain region and directly below the gate electrode and directly above the low concentration source/drain region. A semiconductor device according to claim 1.