JPS62190764A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS62190764A JPS62190764A JP3236186A JP3236186A JPS62190764A JP S62190764 A JPS62190764 A JP S62190764A JP 3236186 A JP3236186 A JP 3236186A JP 3236186 A JP3236186 A JP 3236186A JP S62190764 A JPS62190764 A JP S62190764A
- Authority
- JP
- Japan
- Prior art keywords
- mos type
- drain
- region
- present
- semiconductor equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010893 electron trap Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯＳ型ｌＦＥＴのドレイン部構造に関し、と
りわけ外チャネルＭＯＳ型ＩＦＩ！ｉＴのドレイン部構
造に関する〇
〔発明の概要〕
本発明は、半導体装置に関し、ＭＯＳ型１１’ｌ！！Ｔ
の少くともドレイン部に於て・ゲート下のチャネル部と
連らなる形でＰ領域が形成されて成る事を特徴とする＠
〔従来の技術〕
従来、ＭＯＳ型ＦＢＴは、第２図に示す如き構造をとっ
ているのが通例であった。すなわち、８１基板１の表面
には、ゲート酸化膜１２、ゲート電極１３、ソース拡散
領域１４、ドレイン拡散領域１５と、少くとも該ドレイ
ン拡散領域とチャネル部を連らなる形でＬ Ｄ Ｄ （
Ｌｉｇｈｔｌｙ ＤｏｐｅｄＤｒａｉｎ）部１６及び
バリッド・チャネル部１７が形成されて成るのが通例で
あった。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of the drain part of a MOS type IFET, and particularly to an outer channel MOS type IFI! 〇 [Summary of the Invention] The present invention relates to a semiconductor device, and relates to a MOS type 11'l! ! T
[Prior art] Conventionally, a MOS type FBT is shown in Fig. 2. It was customary to have a structure like this. That is, on the surface of the 81 substrate 1, there are formed a gate oxide film 12, a gate electrode 13, a source diffusion region 14, a drain diffusion region 15, and an LDD (
Typically, a lightly doped drain section 16 and a valid channel section 17 are formed.
しかし、上記従来技術によると、バリッド・チャネル構
造及びＬ’ＤＤ構造を採用することによりホット・エレ
クトロンのトラッピング現象によるしきい値電圧の変動
を抑止することが行われているのではあるが、その抑止
効果が充分でないという問題点があった。However, according to the above-mentioned prior art, fluctuations in threshold voltage due to hot electron trapping phenomenon are suppressed by adopting a valid channel structure and an L'DD structure; The problem was that the deterrent effect was not sufficient.
本発明はかかる従来技術の問題点をなくし、ホット・エ
レクトロンのトラッピング現象によるしきい値電圧の変
動を最小限におさえるＭＯＳ型ＦＩＴのドレイン部構造
を提供する事を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems of the prior art and to provide a drain structure of a MOS type FIT that minimizes fluctuations in threshold voltage due to hot electron trapping phenomenon.
上記目的を達成するための本発明の基本的な構成は、Ｍ
ＯＳ型ＦＩＩＣＴの少くともドレイン部のチャネル部と
連らなる部位にＰ＋領域を設ける手段をとる。The basic configuration of the present invention to achieve the above object is as follows:
Measures are taken to provide a P+ region at least in a portion of the drain portion of the OS-type FIICT that is continuous with the channel portion.
、本発明の如（ＭＯＳ型’ＦＩＴに於て、少くともドレ
イン部に於てチャネル部と連ら成る形でＰ＋領域を設け
る事により、チャネル部のピンチ・オ＋
７点で発生するホット・エレクトロンｔｔ前記Ｐ領域に
存在するマジョリティー・キャリアであるホールと中和
され、グー）Ｓｉｎ、膜中のトラップｅセンターへのホ
ット壷エレク゛トロンのトラップを減少させる作用があ
る。According to the present invention (in a MOS type FIT, by providing a P+ region at least in the drain part in a continuous manner with the channel part, the hot The electrons are neutralized with holes, which are the majority carriers existing in the P region, and have the effect of reducing the trapping of hot pot electrons to the trap center in the film.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示すＭＯＳ型ＦａｎＴの構
造図である０すなわち、８１基板１０表面には、ゲート
酸化膜２、ゲート電極３・ソース拡散領域４、ドレイン
拡散領域５、ＬＤＤ部６、バリッド・チャネル部７が形
成され、該バリッド・チャネル部と連らなる形で、ドレ
イン部のＬＤＤ部６０表面２は内部にＰ＋領域８を形成
して成る・〔発明の効果〕
上記の如（、ＭＯＳ型ＩＦＩＩＣＴに於て、ドレイン部
のチャネル部と連ら成る型でＰ領域を形成することによ
り、ＭＯＳ型ＩＰＫ’［’のホット畢エレクト四ンのト
ラッピングによるしきい値電圧の変動を最少限に抑制で
きる効果がある。FIG. 1 is a structural diagram of a MOS type FanT showing an embodiment of the present invention. In other words, on the surface of an 81 substrate 10, a gate oxide film 2, a gate electrode 3/source diffusion region 4, a drain diffusion region 5, an LDD A portion 6 and a valid channel portion 7 are formed, and the surface 2 of the LDD portion 60 of the drain portion is formed with a P+ region 8 inside thereof in a form continuous with the valid channel portion. [Effects of the Invention] The above. As shown in (In MOS type IFIICT, by forming the P region in a type that connects the drain part with the channel part, the threshold voltage due to trapping of the hot-hole electric current of MOS type IPK'[') can be reduced. This has the effect of minimizing fluctuations.
第１図は本発明の一実施例を示すＭＯＳ型′Ｆ１！ＸＴ
の構造図、第２図は従来技術によるＭＯＳ型７ＩＴの構
造図を示す。
１．１１・・・・・・Ｓ１基板
２．１２・・・・・・グー）Ｓｉｎ、膜３．１３・・・
・・・ゲート
４．１４・・・・・・リース
５．１５・・・・・・ドレイン
６．１６・−・・・・ＬＤＤ部
７．１７・・・・・・バリッド・チャネル部＋
８・・・・・・Ｐ領域
以 上
出願人 セイコーエプソン株式会社
第１図
第乙図FIG. 1 shows a MOS type 'F1!' showing an embodiment of the present invention. XT
FIG. 2 shows a structural diagram of a MOS type 7IT according to the prior art. 1.11...S1 substrate 2.12...Goo) Sin, film 3.13...
... Gate 4.14 ... Lease 5.15 ... Drain 6.16 ... LDD section 7.17 ... Valid channel section + 8・・・・・・P area and above Applicant Seiko Epson Corporation Figure 1 Figure B
Claims (1)
のチャネル部と連らなる形でＰ＾＋領域が形成されて成
る事を特徴とする半導体装置。A semiconductor device characterized in that a P^+ region is formed in at least a drain part of a MOS type FET so as to be continuous with a channel part under a gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61032361A JP2638776B2 (en) | 1986-02-17 | 1986-02-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61032361A JP2638776B2 (en) | 1986-02-17 | 1986-02-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62190764A true JPS62190764A (en) | 1987-08-20 |
| JP2638776B2 JP2638776B2 (en) | 1997-08-06 |
Family
ID=12356816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61032361A Expired - Lifetime JP2638776B2 (en) | 1986-02-17 | 1986-02-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2638776B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02122567A (en) * | 1988-10-31 | 1990-05-10 | Nec Corp | Semiconductor integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6223168A (en) * | 1985-07-24 | 1987-01-31 | Hitachi Ltd | semiconductor equipment |
-
1986
- 1986-02-17 JP JP61032361A patent/JP2638776B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6223168A (en) * | 1985-07-24 | 1987-01-31 | Hitachi Ltd | semiconductor equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02122567A (en) * | 1988-10-31 | 1990-05-10 | Nec Corp | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2638776B2 (en) | 1997-08-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |