JPS62219662A - Amorphous silicon thin film transistor matrix array - Google Patents

Abstract

PURPOSE:To prevent dielectric breakdown due to static electricity, and to remove a short circuit between bus lines by connecting each drain bus, respective gate bus and these both buses by a-Si films to which an impurity is doped. CONSTITUTION:Each drain bus D as leading-out electrodes from a drain electrode, respective gate bus G as leading-out electrodes from a gate electrode and the drain buses and the gate buses are connected by an a-Si film 27 to which an impurity is doped. Each drain bus D, respective gate bus G and these both buses D, G are connected by an N<+> a-Si film as the a-Si film, to which phosphorus is doped, in the peripheral leading-out sections (shaped parts in the figure) of the drain buses D and the gate buses G. That is, an SiN film 23, an a-Si film 24 and the N<+> a-Si film 27 are shaped onto a glass substrate 21 in succession, and the drain buses Dn, Dn+1 as Al films are formed onto the film 27. The N<+> a-Si film 27 is shaped from the upper sections of the gate buses Gn, Gn+1 formed onto the glass substrate 21.

Description

[Detailed Description of the Invention] [Summary] The present invention aims to prevent dielectric breakdown due to static electricity that occurs during the manufacturing process in a matrix array of thin film transistors (hereinafter referred to as TPT) using a-3T (amorphous silicon). In order to prevent this, impurity-doped a-Si (n"a-Si or p"a-S
i) By connecting each gate bus, each drain bus, and both of these buses with a film, static electricity generated in each bus is removed via the impurity-doped a-Si film. It is.

[Industrial application field]

The present invention relates to TPT used for driving EL and liquid crystal display devices, etc.
The present invention relates to a matrix array, particularly a TPT matrix array using an a-3T film as a semiconductor film.

In an active matrix display panel in which TPT is added to each pixel, the matrix must be manufactured without defects. There are two types of defects: open path lines and short circuits between path lines. In particular, a short circuit between pass lines is a serious defect in which even if one TPT is shorted, the entire line becomes defective.
It is necessary to manufacture T without shorting.

The main cause of the above-mentioned short circuit is breakdown of the insulating film due to static electricity generated during the matrix manufacturing process or subsequent processes. Therefore, there is a need for means to prevent electrostatic damage during each process.

[Traditional technique]

The structure of a liquid crystal display panel to which a conventional TPT matrix array is applied is shown in Figure 4 (al), and an enlarged view of the TPT portion (inside the circle) is shown in the same figure (bl). A glass substrate 4 formed in a matrix of a TPT 2 and a transparent display electrode 3 driven by the TPT 2, a liquid crystal N5, a transparent electrode 6, a color filter 7, a glass substrate 8, and a polarizing plate 9 are sequentially attached. It has a layered structure.Then, the drain electrode 2 of TPT2
From d, a drain bus D is connected as an extraction electrode for each line.
A gate bus G is pulled out from the gate electrode 2g as an extraction electrode for each line, and the data driver 10 and the scan driver 11 drive the active drive of each pixel via the drain bus D1 and the gate bus G, respectively. will be held.

Next, the manufacturing process of the TPT 2 in the liquid crystal display panel is shown on the left side of FIG. 5, and the manufacturing process of the peripheral 'JI part of the drain bus D, which proceeds simultaneously with the above manufacturing process, is shown on the right side of FIG.

First, as shown in FIG. 1al, the glass substrate 21 (the fourth
(equivalent to the glass substrate 4 in the figure) with a thickness of 1 made of Cr etc.
000 gate electrodes 22 are formed.

This gate electrode 22 also serves as a gate bus drawn out to the outside of the glass substrate 21. Furthermore, from above, 5
Using the plasma CVD method using iHa gas as a base gas, a SiN film 2 with a thickness of 3,000 nm was fabricated as a gate insulating film.
3. A-Si film 24 with a thickness of 1000 nm as a semiconductor film
, a SiO2 film with a thickness of 1000 nm as a protective film is successively formed.

In FIG. 2B, the SiO2 film 25 is selectively etched by burning the photoresist 26 on the S'i02 film 25 and above the gate electrode 22. Leave the photoresist 26 as it is (.

In the same figure (C1, an na-Si film 2 doped with P (phosphorus) is placed on the a-3T film 24 and the photoresist 26.
7 at a substrate temperature of 120°C using plasma CVD method.
After forming 00 layers, 1000 layers of A1 film 28 are formed by vacuum evaporation at room temperature. Thereafter, the photoresist 26 is removed by immersing it in a resist stripping solution such as acetone, as shown in FIG.

Next, the photoresist 29 is patterned again to form a drain electrode and a source electrode, and as shown in el of the same figure, the excess film 8 is removed by etching with phosphoric acid.

Leave the photoresist 29 as it is and now apply CF4
By performing 02-based gas plasma etching, the n''a-Si film 27, the a-Si film 24, and the SiN film 2 formed in areas other than under the photoresist 29 are removed.
Remove 3. Thereafter, by removing the photoresist 29, TPTs as shown on the left side of the figure (fl) are separated and formed. At this time, the Aβ film 28 formed above the left and right sides of the gate electrode G is It becomes the drain electrode and source electrode.

Also, Aj! The film 28 also serves as a drain bus, and as shown on the right side of FIG.

In the subsequent process, a glabellar insulating layer is formed on the TFT, contact holes are provided, and each TPT is connected to each pass line using metal to form a matrix. After that,
Depending on the purpose, it goes through a liquid crystal or EL manufacturing process.

[Problem that the invention seeks to solve]

In the conventional TPT matrix array, as described above, the gate buses, the drain buses, and both buses are separated from each other. Therefore, high voltage static electricity (several 100 to several KV) is generated during the matrix production process or subsequent processes.
is applied between each bus, and as a result, the gate insulating film (fifth
There was a problem in that dielectric breakdown of the SiN film 23) in the figure occurred, resulting in a short circuit between the drain bus and the gate bus.

As mentioned above, such a short circuit between the path lines causes 1
Even a short circuit within one TFT is a serious defect that can cause the entire line to become defective.

An object of the present invention is to provide a TPT matrix array that can prevent dielectric breakdown caused by static electricity and eliminate short circuits between pass lines.

[Means for solving problems]

The present invention provides impurity-doped a-Si[%(n”a
-3t film or p''a-Si film).

[For production]

The above n"a-Si film (or p"a-Si film) acts as a low resistance that allows high voltage (several 100s to several KV) static electricity to escape. In response to voltages (several tens of volts) sometimes applied from external circuits (data driver, scan driver), they act as large resistances that have no influence on each other. Therefore, the above n''a-Si film (or p''a-Si film)
Application of static electricity as described above is prevented, and dielectric breakdown of TPT can be prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view schematically showing an embodiment of the present invention. In the same figure, =9- is omitted for the matrix part M, but here, a large number of TPTs are arranged in a matrix like the one shown in FIG.
The configuration of T is also the same as that in FIG. 4 1bl. The feature of this embodiment is that in the peripheral lead-out portions of the drain bus D and gate bus G (the shaded area in FIG. 1), between each drain bus 0,
Between each gate bus and between these buses D and G, P
(phosphorous) doped a-8i film n” a-
It is located at a point connected by a Si film.

Therefore, an enlarged cross-sectional configuration of the peripheral lead-out portions of the drain bus D and gate bus G as seen from the directions of arrows A and B in FIG. 1 is shown in FIG. 2 (al and (bl). SiN film 23 and a-Si film 24 on 21
and the above-mentioned n”a-Sill! 27 are sequentially formed,
The configuration is such that drain buses I)n and Dn++, which are AA films, are provided on the n''a-Si film 27. That is, adjacent drain buses Dn.

pn+1 are connected to each other by the n''a-Sil layer 27, and are not separated as shown in FIG. 5 if) described above.

On the other hand, in Fig. 2), n''a-Si is
This is a structure in which a film 27 is formed. That is, the adjacent gate buses Gn+ Gna+ are connected to each other by the n"a-Si film 27. Furthermore, the n"a-Si film 27 on the drain bus side shown in FIG. The n''a-3S film 27 on the gate bus side shown in FIG. 1B is connected to each other at one end as indicated by diagonal lines in FIG. ``This means that they are connected by the a-3L film 27.

Next, an example of the manufacturing method for realizing this embodiment will be described in the third section.
As shown in the figure. Note that the left side of the figure shows the manufacturing process of the TPT, and the right side shows the manufacturing process of the peripheral drawer part of the drain bus D, which proceeds simultaneously with the above process.

Here, the steps (a) to (e) in FIG.
Since it is the same as that shown in e), its explanation will be omitted here. However, when forming the film by the plasma CVD method as shown in FIG. Make sure to wear a mask.

Then, n by the plasma CVD method in the same figure (e)
``When forming the a-3L film 27, the above mask is removed and the second
As shown in Figure (b), an n"a-Si film 27 is directly formed on the gate bus G (Gn, G). At this time, the n"a-3t film 27 on the gate bus side and the drain bus side n+a-SiI! 1127 are connected at one end.

In this way, the excess Al film 8 is etched (
After completing the process up to step (e) in Figure 3, the subsequent CF41
In the gas plasma etching process of the 02 series, the same figure (
As shown in f), the peripheral lead-out portion on the drain bus side is covered with a metal mask 30.

In this way, n” below the metal mask 30
a-3t membrane 27. a-3t membrane 24. The SiN film 23 etc. are
It remains as it is without being etched by the active species of CFa. By subsequently removing the photoresist 29, the adjacent drain buses D111Drm are connected to each other by the n''a-3L film 27, as shown in FIG. The configuration shown in FIGS. 1 and 2 can be adopted.

Here, the resistance value of the n''a-3t film 27 formed between each pass line in the peripheral lead-out portion can be adjusted within a certain range, and is preferably about 1 to several tens of MΩ.For example, the n''a- SilI! Assuming that the resistivity of I is 10 ΩG, the film thickness is 500, the interval between each pass line is 100 μm, and the connection length is 1.0 cm, the above resistance value is 20 MΩ.

The n''a-Si film 27 having such a resistance value acts as a low resistance that allows high voltage (several 100 V to several KV) static electricity to escape.

Therefore, static electricity generated in each bus during the matrix array manufacturing process is removed by the n''a-Si film 27, and dielectric breakdown of the TPT is prevented.

On the other hand, since the voltage applied to each bus from the external circuit (data driver 10 and scan driver 11 shown in FIG. 4 (δ)) during driving is about several tens of volts, the above n''a- The Si film 27 acts as a large resistance. That is, during driving, each bus is insulated as in the conventional case, and the n"a-Si film 27 has no effect on the external circuit. do not have.

Note that the n''a-Si film 2 is used to connect each bus.
Instead of using 7, a-S doped with B (boron) etc.
A p''a-3L film, which is an i film, may also be used.

In addition, the n"a-Si film (or p"a
-Si film) does not necessarily have to be connected to the peripheral lead-out section, for example, the matrix section M shown in Fig. 1.
It may be within.

〔Effect of the invention〕

According to the present invention, static electricity generated in the gate bus and drain bus during the fabrication process of the matrix array can be reduced by using n”a-Si.
Since it can be removed by a film (or a p''a-Si film), dielectric breakdown due to the above-mentioned static electricity can be prevented, and an amorphous silicon thin film transistor array without short circuit defects can be realized.

[Brief explanation of drawings]

Figure 1 is a schematic plan view showing one embodiment of the present invention, Figure 2 +
8), (b) are enlarged cross-sectional views showing the structure of the peripheral drawer part in the same embodiment; FIGS. 3+a) to [g) are manufacturing process diagrams showing an example of the manufacturing method for realizing the same embodiment; FIG. 4(b) is a configuration diagram showing a conventional general liquid crystal display panel, and FIGS. 5(a) to (f) are manufacturing process diagrams showing a conventional method for manufacturing a TPT matrix array. 21...Glass substrate, 23...SiN film (gate insulating film), 24...a-
3t film (semiconductor film), 27...n1a-8iI! 1111 30...Metal mask, D, Dn, Dh+1...Drain bus, Gy Gn
,(),n++・,,Gatehas.

Claims (5)

[Claims] (1) Insulating substrate (2) with gate electrode (22) formed
1) A gate insulating film (23), an a-Si semiconductor film (24), and an a-Si film (27) doped with impurities are formed on the top.
), and a source electrode (28) and a drain electrode (28) are further formed on the impurity-doped a-Si film, and a large number of thin film transistors are integrated in a matrix. In, between each drain bus (D) which is an extraction electrode from the drain electrode, between each gate bus (G) which is an extraction electrode from the gate electrode, and between the drain bus and the gate bus, Impurity-doped a-Si film (2
7) An amorphous silicon thin film transistor matrix array characterized by being connected by. (2) The impurity-doped a-Si film is n^+a-Si
The amorphous silicon thin film transistor matrix array according to claim 1, wherein the amorphous silicon thin film transistor matrix array is a film. (3) The impurity-doped a-Si film is p^+a-Si
The amorphous silicon thin film transistor matrix array according to claim 1, wherein the amorphous silicon thin film transistor matrix array is a film. (4) According to any one of claims 1 to 3, the resistance value between the buses connected by the impurity-doped a-Si film is 1 to 10 MΩ. The amorphous silicon thin film transistor matrix array described. (5) Each bus has a peripheral portion doped with the impurity.
- The amorphous silicon thin film transistor matrix array according to any one of claims 1 to 4, wherein the amorphous silicon thin film transistor matrix array is connected by a Si film.