JPH01102525A - Thin film transistor array and liquid crystal device using said array - Google Patents

Abstract

PURPOSE:To obtain a TFT array of a simple structure with the least stage and a low fraction defective by incorporating double layers of tantalum oxide and silicon nitride as a constituting element of the dielectric material of a thin film capacitor. CONSTITUTION:This thin film transistor array is constituted by providing the double layers of the tantalum oxide and silicon nitride as the dielectric material of the capacitor. The thin film transistor array having the simple constitution is realized by laminating the tantalum oxide and silicon nitride successively on the gate electrodes and picture element electrodes separated and formed on the same plane is such insulating layers are used. In order to prevent an increase in the resistance of transparent electrodes by the direct contact of the transparent electrodes and TaOH, the structure to provide gate electrodes on the transparent electrodes is preferably adopted. The TFT array of a good yield is thereby formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a structure of a thin film transistor array having thin film transistors and a storage capacitor, and an active matrix liquid crystal display device using the thin film transistor array.

Conventional technology In recent years, thin film transistor arrays using amorphous silicon (hereinafter abbreviated as aSi) can be made large in area at low temperatures.
Due to its excellent stability, it is actively being applied to liquid crystal display substrates and image sensors. This aS
SiNx is attracting attention and being put into practical use as an insulating layer that forms a good interface with i. Further, the dielectric material of the storage capacitor formed at the same time uses SiO2 or SiNx, which have a small dielectric constant.

The gate metal is Ta and the gate insulating film is Ta in order to prevent short circuit between the TPT gate and source/drain.
205 (anodized film)/SiNx, a as a semiconductor
Thin film transistors using Si were developed in the special leap year 1986-147.
It is disclosed in No. 09. Furthermore, Ta205 with a high dielectric constant is being considered as a capacitor, but its leakage current is an issue. It is disclosed in Japanese Patent Publication No. 57-45968 that a stable capacity can be achieved by the structure of Ta205/S i Nx.

Problems to be Solved by the Invention The dielectric constants of SiO2 and SiNx, which are the storage capacitor dielectrics of the conventional TPT array mentioned above, are 3.5.6, respectively.
It is 4. Also, to make a film without pinholes, 200O
A or higher is required. In order to obtain a desired capacitance value with conventional SiO2 and SiNx, it is necessary to increase the area of the capacitor part in the picture element unit, and a bright liquid crystal display substrate cannot be obtained.

Also, S forms a good interface with (amorphous) aSi.
A TPT using iNx as a gate insulating layer has a drawback that its on-current is smaller than a single-crystal Si MOS. Furthermore, when applied to liquid crystal display devices, it is desired to further reduce the off-state current.

Also, when forming SiNx, the raw material gas is NH3°S
Since a reducing gas such as iH4 or H2 is used, if the display electrode is a transparent electrode, the transparent electrode will be attacked.

Specifically, there are adverse effects such as a decrease in the transmittance of the transparent electrode, and an increase in lateral leakage current due to decomposition and destruction of the pattern. As shown in FIG. 4, in order to prevent this, it is necessary to protect the transparent electrode with an oxide such as SiO2 and then form SiNx. Such a configuration has the disadvantage that the array configuration and manufacturing process become complicated. In addition, in order to obtain good contact with the source and drain metals of thin film transistors, native oxide on ASI was used.
However, the etching solution also etches the SiNx insulating layer, so if there are pinholes in the resist or other mask, pinholes will form in the SiN, causing short circuits. . The difference in level between the contact hole between the source/drain metal and the transparent electrode is large, causing a problem in coverage of the source/drain metal.

The picture element electrode as shown in Fig. 4 is 5i-02 with a small dielectric constant.
A liquid crystal display device in which SiNx is protected has the disadvantage that the driving voltage is higher than that in a case in which ITO is exposed.

In view of the above, an object of the present invention is to provide a TFT array with a simple structure, fewer steps, and a lower defect rate, and a bright liquid crystal display device using the TFT array, which is bright and has a low driving voltage.

Means for Solving the Problems The present invention consists of a thin film transistor provided on an insulating substrate, a pixel electrode connected to the source (or drain) electrode of the thin film transistor, and a thin film capacitor connected to the pixel electrode. This thin film transistor array includes a double layer of tantalum oxide and silicon nitride as the dielectric material of the capacitor. This capacitor is a three-layer capacitor with asymmetrical C-v characteristics that is suitable for use as a substrate for liquid crystal display devices, with silicon nitride used as the dielectric material, tantalum oxide on one main surface, and amorphous silicon on the other main surface. is advantageous.

It is preferable that the gate insulating layer of the thin film transistor be a double layer of tantalum oxide and silicon nitride, which constitute the thin film capacitor.

By using the insulating layer of the present invention, a thin film transistor array with a simple structure can be realized by sequentially laminating tantalum oxide and silicon nitride on a gate electrode and a pixel electrode that are formed separately on the same plane. In order to prevent the transparent electrode from directly contacting TaOx and increasing the resistance of the transparent electrode, it is preferable to provide a structure in which a gate metal is provided on the transparent electrode.

If the film thickness of tantalum oxide is made larger than the film thickness of the gate electrode, the gate electrode can be covered.
It is preferable to form Nx with a thickness of 1000A or more.

In summary, the present invention stacks TaOx/SiNx on a patterned gate electrode and a patterned cutting electrode, forms patterned aSi on TaOx/SiNx, and further forms a patterned source/drain electrode. It is an active matrix substrate formed with T
aox/S i Nx functions as a gate insulating layer in the thin film transistor section, a dielectric layer in the capacitor section, and a protective layer on the picture element electrode of the transparent electrode.

Function: The dielectric constants of SiNx and TaOx constituting the insulating layer of the present invention are 6.4.22, respectively, which is higher than that of conventional SiNx and S
Compared to an insulating layer composed of 6.4.3.5 of iO2, the capacitance becomes larger at the same film thickness. For example, T
The effective dielectric constant of aOx (200OA)/5iNx (200OA) is 10.5.

This layer with a high dielectric constant becomes a gate insulating layer in the TFT section, and can have a larger on-state current than a TPT of the same size. Furthermore, a good SiNx/aSi interface can be maintained.

In the storage capacitor section, the capacitance value increases with the same area. Furthermore, leakage current was reduced compared to a TaOx single layer. TaOx/SiNx roughly functions as a protective layer for the picture element electrode.

Since the dielectric constant is high, the voltage loss in a protective insulating layer of the same thickness is reduced, and the voltage required to drive the liquid crystal can be reduced.

In addition, T a Ox/S i N was applied directly on the transparent electrode.
Since the insulating layer x can be provided, the level difference in contact with the transparent electrode can be reduced. This reduced the contact failure rate.

Furthermore, when TaOx and a transparent electrode are brought into direct contact, a high-resistance layer is formed in a subsequent high-temperature process. For this reason, contact resistance increases, and the present invention solves this problem by interposing a gate metal.

In the storage capacitor section, in the simplification process described later, gate metal / T a Ox / S i Nx / a
The MIS structure is Si/n"aSi/source metal. This C-v characteristic is shown in Figure 4. The voltage across the liquid crystal is kept constant at Vsc, and the voltage at the pixel electrode is between Vgd and Vgd-. The liquid crystal is AC driven while maintaining the voltage at Vgd, but the Vgd value is 0, which tends to reduce the TPT's off resistance.
When the voltage is close to Vgd-, the capacitance value increases to compensate for variations in off-resistance.

Example Examples will be described below using plan views and cross-sectional views.

- (Embodiment 1) This is a method of realizing an active matrix circuit having picture element units (indicated by broken lines) of the equivalent circuit shown in FIG. 111
112 is a gate line, 112 is a source line (or drain line), 113 is a previous stage gate line, 114 is a transistor, 115 is a load capacitor such as a liquid crystal, and 116 is an auxiliary capacitor connected to the previous stage gate line. Figure 1 (a
) is a final plan view, and FIG. 1(b) and FIG. 1(c) are sectional views taken along line AA' and line BB' in FIG. 1(a). The process will be explained below using this figure.

(1) 1 layer of ITO was deposited on a glass substrate lO by DC sputtering.
Deposit 000A. Figure 1(a) shows the transparent conductive layer ITO.
A gate electrode made of ITOlla shown by a broken line, ITOll
Etching is performed so as to leave the shape of a picture element electrode made of lb.

(2) 12a of ECR to deposit 1000A of Cr metal layer
Etching is performed so that the protective electrode 12b in the contact hole portion is left on the picture element electrode 11b as a gate electrode made of the same. FIG. 1(a) shows a Cr electrode 12a,
12b pattern is shown.

(3) TaOx layer 15 of 200OA by reactive sputtering method
Deposit.

(3) 5iNxF as an insulating layer using plasma CVD method!
13 at 2000 A, a S i Fj as the semiconductor layer
14 at 500A% Si Nx layer 18 at 1000A
accumulate.

(4) Etch the layer 5iNx18 which will become the channel protection layer so as to leave it in the shape of patterns 18a and 18b shown in FIG. 1(a).

(5) Deposit an impurity-doped n''aSi layer 16 of 50 OA by plasma CVD.

(6) Layer 16.14.13.1 using CF4 and 02 in the patterns 50a and 50b in FIG. 1(a).
5 is dry etched to form a contact hole.

(7) MoSi219 was heated to 500 A by DC sputtering.

Deposit At 17 at 7000A.

(8) Etch the layers 17 and 19 so as to leave the patterns of the source (or drain) electrode 17a, drain (or source) electrode 17b, and storage capacitor electrode 17c in the pattern shown in FIG. 1(a).

When etching MoSi219 under AI, 17
a% 17b% n+asi16 and l? of the exposed part not covered by the 17c pattern. a, 17
b, 17c, 18a, aS iF of the area other than under the patterns of 18b! etching.

As shown in the figure, it is double layered with a gate electrode and a transparent electrode.
No gate disconnections occurred.

In this embodiment, an active matrix substrate can be formed using five masks. Since the picture element electrode is transparent, it is used in transmissive liquid crystal displays and the like.

(Example 2) Figure 2(a) is the final plan view, Figure 2(b), Figure 2(c)
) is a sectional view taken along line cc' and line DD' in FIG. 2(a). The process will be explained below using this figure.

In Example 1, the exposed glass substrate is aSi or SiN.
When etching x, about 1000 OA is etched at the same time, causing problems such as uneven alignment of the liquid crystal. Therefore, in this example, before step (1) of Example 1, 200% SiO220 was deposited on the base glass substrate 10 by atmospheric pressure CVD.
0A is formed.

Compared to glass substrates, SiO2 is more resistant to etching gases and etching solutions during processing. In this way, the base glass substrate was only etched by 1000A. Further, in step (4) of the first embodiment, in this embodiment, a layer 18 serving as a channel protection layer is left in a pattern 18b at the intersection of the source pass line and the gate pass line, as shown in FIG. 2(a). In this way, the probability of occurrence of short circuits at the intersection of the source path line and the gate path line is reduced. Furthermore, the process of Example 1 (
6), layer 16.14.13 using CF a and 02 as shown in pattern 20 of FIG. 2(a).
．． Dry etching 15.

In this way, the picture element electrode ITO becomes exposed and the operating voltage can be lowered. Cr on the picture element electrode
If no voltage is left, the operating voltage will rise by about 0.2V.

In the above-mentioned embodiment, a method was shown in which the gate electrode was formed on ITO and the gate wiring was formed using Cr metal, but instead of ITO, 5 nap, CdO was used as a transparent electrode.

There are ZnO, etc. The metal on the transparent electrode should be selected from a material that can withstand the etching agent of the semiconductor layer and the insulating layer.
Examples include Cr, Mo, TiN, and silicide. Furthermore, the gate metals are 2 such as AI and MoSi2, AI and TiN, etc.
It does not matter if it consists of more layers than types.

(Example 3) Using the TPT array created in Example 1 as one substrate, 5
．． A liquid crystal panel is prepared by holding a substrate having a transparent counter electrode with a gap of 5 μm and injecting liquid crystal into the gap. The image characteristics of this liquid crystal panel are as follows. FIG. 5(b) shows a cross-sectional view of the pixel electrode portion of the TPT array prepared in Example 1 together with a conventional example.

Compared to the conventional case shown in FIG. 5(a), in the case of the present invention shown in FIG. 5(b), the dielectric constant of the insulating film on the display electrode is larger.
The effective voltage applied to the liquid crystal increases. Therefore, the driving voltage is 4. IV.

It becomes 3.6v.

The magnitude of the flicker component, which indicates the degree of flickering on the screen, is the ratio of the intensity of the 30 Hz vibration component of the transmitted light to the DC component of the transmitted light, and in the conventional example, it is 2. 0%, in the example of the present invention 1. It is 0%.

Effect 1 of the invention: Electrical properties: Since an insulating layer with a high relative dielectric constant is used, the electric field strength at the semiconductor interface becomes large, and the on-current hole and off-current of the TPT become small. The broken line in FIG. 6 indicates that the gate insulating layer is Si
NX (400OA), solid line is Ta0x (200OA)
/5iNx (200OA) are shown in FIG. 6 by broken lines and solid lines, respectively. T Box (2
00OA) / S i Nx (200OA) TP
The on/off transition of T is steep, and the difference in brightness between the top and bottom of the screen of a liquid crystal display device can be greatly improved by using a TPT array substrate using this TPT. In addition, TFTs that obtain the same on-current
The W/L can be made smaller, and the off-state current can be made even smaller.

2. Image characteristics of the liquid crystal panel ``The area of the capacitor section and the area of the TFT section using this insulator may be small. The display electrode can be made larger and a brighter LCD can be realized.

[Since the dielectric constant of the TO protective film TaO/S i N x is large, most of the applied voltage is applied to the liquid crystal, and the operating voltage can be reduced.

Furthermore, flicker is also reduced.

3. Structure The insulating oxide layer protecting the transparent electrode is TaOx in the present invention.
, in the conventional example, is SiO2. The height difference of the contact hole is 400OA and 6000A respectively.
PT arrays can easily make contact with transparent electrodes, and the incidence of defects due to poor contact has been halved compared to conventional methods.

4. Process TaOx is hardly etched by the HF-based etching solution for SiNx and aSi, so even if there are pinholes in 5iNX and aSi, there will be almost no short-circuit defects between the gate metal and source/drain metal, and the capacitance portion will be completely etched. The incidence of point defects due to short circuits has also been reduced.

The present invention discloses the structure and manufacturing method of a TPT array with high yield. A liquid crystal panel using this TPT array also has excellent image characteristics.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of the TPT array of Example 1 of the present invention, and FIGS. 1(b) and 1(C) are 8-A' and B- of FIG.
B' line sectional view, FIG. 2(a) is the TP of Example 2 of the present invention
A plan view of the T array, same (b). (c) is a cross-sectional view taken along lines CC' and D-D' of (a), and the third
The figure is an equivalent circuit diagram of an embodiment of the present invention, Figure 4 is a CV characteristic diagram, and Figures 5 (a) and (b) are cross-sectional views of l picture elements of a conventional TPT array and a TFT array of the present invention. , FIG. 6 is a transistor characteristic diagram of a conventional TPT array and a TPT array of the present invention. . 11...Transparent electrode, 12...Metal layer, 12a.
Gate pass line pattern, 12b... Gate metal pattern on picture element electrode, 15. -TaOx, 13.
・51N×117C... One electrode pattern of storage capacitor. Name of agent Patent attorney Toshio Nakao (1 person) Figure 1 (b) (CJ Figure 2 (b) <C) Figure 5 (Q) (bJ OIj Figure 3 Figure 4 gd

Claims (17)

[Claims] (1) In a thin film transistor array including as constituent elements a thin film transistor provided on an insulating substrate, a picture element electrode connected to a source (or drain) electrode of the thin film transistor, and a thin film capacitor connected to the picture element electrode, A thin film transistor array comprising a double layer of tantalum oxide and silicon nitride as a dielectric material of the thin film capacitor. (2) Claims characterized in that the dielectric material of the thin film capacitor includes as a component a triple layer of silicon nitride, tantalum oxide on one main surface and amorphous silicon on the other main surface. 2. The thin film transistor array according to item 1. (3) The thin film transistor array according to claim 1 or 2, wherein the gate insulating layer of the thin film transistor includes a double layer of the tantalum oxide and the silicon nitride as constituent elements. (4) Claims 1, 2, and 3 characterized in that one electrode of the thin film capacitor is a gate electrode.
3. The thin film transistor array according to any one of the items. (5) A gate electrode and a picture element electrode are formed separately on the same plane, and the tantalum oxide and the silicon nitride are sequentially laminated on the gate electrode and the picture element electrode. The thin film transistor array according to any one of the first term, the second term, the third term, and the fourth term. (6) Claims 1, 2, 3, 4, and 5, characterized in that the gate electrode is formed at least in part from a material constituting a picture element electrode. The thin film transistor array according to any one of the above. (7) Claims 1, 2, 3, 4, and 5, characterized in that a material constituting a gate electrode is formed on a part of the picture element electrode. , the thin film transistor array according to any one of Item 6. (8) The film thickness of tantalum oxide is larger than the film thickness of the gate layer,
Claims 1, 2, 3, 4, 5, 6, and 7, characterized in that the silicon nitride film has a thickness of 1000A or more. thin film transistor array. (9) Claims 1, 2, 3, and 4, characterized in that SiO_2 is deposited on the substrate.
The thin film transistor array according to any one of Items 5, 6, 7, and 8. (10) In a thin film transistor array including, as constituent elements, a thin film transistor provided on an insulating substrate, a picture element electrode connected to the source or drain electrode of the thin film transistor, and a thin film capacitor connected to the picture element electrode, the capacitor's dielectric 1. A liquid crystal display device comprising a thin film transistor array comprising a double layer of tantalum oxide and silicon nitride as a body material. (11) A thin film transistor array characterized in that the dielectric material of the capacitor includes a triple layer of silicon nitride with tantalum oxide on one main surface and amorphous silicon on the other main surface as a component. A liquid crystal display device according to claim 10, characterized in that: (12) A liquid crystal display device according to claim 10 or 11, characterized in that a thin film transistor array is used in which the gate insulating layer of the thin film transistor includes a double layer of the tantalum oxide and the silicon nitride as constituent elements. . (13) The liquid crystal display device according to any one of claims 10, 11, and 12, which uses a thin film transistor array in which one electrode of the thin film capacitor is a gate electrode. (14) A thin film transistor array is used, in which a gate electrode and a pixel electrode are formed separately on the same plane, and the tantalum oxide and the silicon nitride are sequentially laminated on the gate electrode and the pixel electrode. A liquid crystal display device according to any one of claims 10, 11, 12, and 13. (15) Claims 10 and 11 use a thin film transistor array in which the gate electrode is formed at least in part from a material constituting a picture element electrode.
13. The liquid crystal display device according to any one of Items 1, 12, 13, and 14. (16) Claims 10, 11, and 1 are characterized in that a thin film transistor array is used in which a material constituting a gate electrode is formed on a portion of a picture element electrode.
The liquid crystal display device according to any one of Item 2, Item 13, Item 14, and Item 15. (17) Claims 10 and 11, characterized in that a thin film transistor array is used in which the film thickness of tantalum oxide is larger than the film thickness of the gate layer and the film thickness of silicon nitride is 1000A or more. The liquid crystal display device according to any one of Items 12, 13, 14, 15, and 16.