JPS62177970A - Manufacture of field-effect transistor - Google Patents
Manufacture of field-effect transistorInfo
- Publication number
- JPS62177970A JPS62177970A JP1945286A JP1945286A JPS62177970A JP S62177970 A JPS62177970 A JP S62177970A JP 1945286 A JP1945286 A JP 1945286A JP 1945286 A JP1945286 A JP 1945286A JP S62177970 A JPS62177970 A JP S62177970A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- forming
- mask
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 17
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 108091093088 Amplicon Proteins 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- 241000287828 Gallus gallus Species 0.000 description 1
- 101100037618 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) ant-1 gene Proteins 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野１
本発明はヘデ）］接合界面にお（″）る高速電子を利用
した電界効果トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application 1) The present invention relates to a method of manufacturing a field effect transistor using high-speed electrons present at a junction interface.
〔従来の技術１
ＧａＡｓと Ａｆｆ ＧａＡｓのへテロ界面の高速な２
次ｊＬ電子チャネルを用いた電界効果トランジスタ（以
下ＦＥＴと記す）は、ＧａＡｓを用いたＦＥＴより更に
高速、高性能の素子として低雑音素子、および高速（（
ｌ’への応用が盛んに研究されている。この２次元電子
チャネルを用いたＦ Ｅ Ｔをさらに高性能化するため
にはソース抵抗の低減が重要であり、この−・例として
、第２図に断面構造で示すように、イオン注入によって
デーｌ−電極１３の外側にｎ゛型不純物領域１６を形成
したものかアイ イーイー イー コニレタｌ−ロシ
−ｒハイス １７クーノ、１ １１ｉ１ｉ１ｉ １ミ
ｌ ｅ ｃ Ｌ ｒ ｕ ｎ Ｉｔ ｅ ｖ ｉ ｃ
ｃ １． ｅ ｔ ｔ ｅ ｒ Ｌ、）第＋−：
Ｉ） ｌ−−５巻 １２０自゛（１９８４年）に報
告さノしている。[Conventional technology 1 High-speed heterointerface of GaAs and Aff GaAs 2
Field-effect transistors (hereinafter referred to as FETs) using next jL electron channels are faster, higher-performance devices than FETs using GaAs, and are low-noise devices and high-speed ((
Applications to l' are being actively researched. In order to further improve the performance of FETs using this two-dimensional electron channel, it is important to reduce the source resistance. Is the n-type impurity region 16 formed outside the l-electrode 13?
-r high speed 17 cuno, 1 11i1i1i 1 mil e c L r u n It e v i c
c1. e t t er L, )th +-:
I) Reported in Vol. 5, 120 (1984).
第２ ［：／ｌにおい゛（５は高抵抗のＧ ａ Ａ Ｓ
Ｖ＆ ４収、１１はアンｌ’−ブＧ ；ｉ Ａ ｓ層
、１２はｎ Ｉｉ！４ Ａｆｆ ＧａＡｓ層、Ｉｌ」耐
熱性のチー１〜電極、１−１Ａｌｔソース電極 １−１
１（は１〜レイン電極で、３は２次九電ｔ ４− 飄・
ネルである。2nd [:/l smell (5 is high resistance Ga A S
V&4 collection, 11 is Anl'-buG; i As layer, 12 is n Ii! 4 Aff GaAs layer, Il” heat-resistant Qi 1~electrode, 1-1 Alt source electrode 1-1
1 (is the 1~rain electrode, 3 is the secondary nine-electrode t 4- 飄・
It's Nell.
このｌ＝’ ｌ＞ Ｔの製ｊ９ｉ−１−程は［１型Ａｆ
ｆｌｉａＡｓ層＋２１−にＷ等の耐熱性ゲート電極１Ｂ
を形成し、こｈをマスクとして例１はｎ Ｌｆ！、 ｌ
〜−バシトどしてＳ１イオンを注入し、熱処理を行右−
）で［１゛型イく鈍物領域１０を形成した後、ソースお
、ＬひＩ・レイシミ極１１Ｉ Ａ 、 １４．１３を
形成するものである、１１発明か解決しよ）とする問題
点ｌ
しかしなかＩ゛１、上述し７た従来のＦ ｆ’： ′Ｆ
の製３青力／Ｊ：、では、頁１型 ＡｐＦｉａＡｓ層１
２のｊグさか数釘オンクストＩ′７−ム（人）と薄いた
め、このような？専い層とアンＩ・−プＧａＡｓ層１１
表面の部分に高１−−スイオシの注入は難しく、小さな
シート抵抗、ずなわＬ）低ソースロ（抗をｆ′）るのは
困難で１１′）ろ、、まｌ・シー）・抵抗を小さくしよ
うとＩ−で深＜ＪＬで注入ずれはソ・−ス、ＦＬ、イン
１迫域となるＮ ｌ ｉｌｌ！ １；１屯１勿＃（ｔ
’Ａ １． ｔ）間（１） ｂ’ｆｉ １ｉｉ１１かＸ
１ｊｕｌ素−１１てはア＞ｌ’ −ｙ”ＧａＡｓ層１
１中へのｌＦ人−Ｌ７育か増入り−る結Ｔ、１・「イン
ニ１シタクタンスのｊ曽入やし、きい電月のシフト秀い
わトノ）る知チャイ・ルな０県を起して１−よ）社い）
問題点かある。まｌｌ活性化の為に高温で（））熱処理
を要するｌ−め、アント−１ＧａＡｓ層ｌ＼小純１勿か
拡散１、結晶晶質ａ）劣化を起・工“問題点もある４、
さらＣ２二、耐熱性のチー１〜電極は比較的抵抗か人き
く、かつ内部応力か人きい／：こめ、ゲート抵抗か増大
し７、ｆバトσ度か成子する恐れＩＪある４、まｌトニ
のｉ、ｘ −）−電極は通常Ｉ・ライエ・／−ｆ・ンタ
（１，二、Ｌ−）で１［構成されるが、ザフミク＋７ン
Ｉにはま／、ｊガ１［−く索子グ）微細化は困り・１「
イノ状ｌＩｌで７する。The production of this l='l> T is [Type 1 Af
Heat-resistant gate electrode 1B made of W etc. on the fliaAs layer +21-
, and using h as a mask, Example 1 is n Lf! , l
~-Inject S1 ions and heat treatment right-
), [After forming the 1゛-shaped blunt region 10, the source, L, I, and reciprocal poles 11I A, 14.13 are formed. l However, I゛1, the above-mentioned conventional F f': 'F
Manufactured by 3 blue power/J:, page 1 type ApFiaAs layer 1
Is this kind of thing because it's as thin as a few nails on the top of 2? Dedicated layer and amplicon GaAs layer 11
It is difficult to inject high 1--silicon into the surface area, small sheet resistance, low resistance (f') and low resistance (11') low resistance. When I- is deep < JL, the injection deviation is source, FL, and in-1 close range N l ill! 1; 1 ton 1 course # (t
'A1. t) between (1) b'fi 1ii11 or X
1jul element -11 is a>l' -y”GaAs layer 1
1F people to 1st - L7 growth or increase - result T, 1. ``J Soiri Yashi of Inni 1 Sitactance, Kii Dengetsu's shift is excellent. te1-yo) company)
There are some problems. However, the ant-1 GaAs layer, which requires heat treatment at high temperatures () for activation, has some problems:
In addition, C22, the heat resistance of the electrode is relatively high, and the internal stress is high. Toni's i, Kusakukog) Miniaturization is a problem・1
7 with ino-like lIl.
本発明ａ）［１的は、ノーＩ・抵抗か低く、知チャオ・
ル効宋を起１３−ことのない１紋細な素ｊ′構造を右す
る電界効果ｌ・ランリスタ０）製造方法を提ＩＩ；４−
ることに、？）る。The present invention a) [1] No I, low resistance, Chichao,
13-The electric field effect that created the fine elemental j' structure that originated in the Song Dynasty 0) Proposed the manufacturing method II; 4-
Especially? ).
ｉ問題点を解決するｔ：めの手段１
本発明の電界効用トランリスタの製造方法は、高抵抗基
板上に高純度の第１の半導体層を形成しな後この第１の
半導体層−１に一導電型不純物を含む１層以上ａ）第２
の蔓１へ導体層を形成する工程と、この第２の半導体層
」−にソース及びＦ Ｌイン領域の開口部を有するマス
クを形成する二丁二程と、前記開１−１部の第２の半導
体層をエッチング１．前記第１の゛ｌ′−導体層を露出
させる工程と、露出した前記第１の半導体層上に前記マ
スクより厚くソース及びトシイン領域となる一導電型高
濃度不純物層を垂直ＩＪ向に形成する上程と、全面に絶
縁膜を被着した後前フＪ性エツチンク法によりこの絶縁
膜をエッチングし前記高濃度不純物層の側面にのみに絶
縁膜を残１− 、Ｉ稈と、前記第２の半導体層上のマス
クを除去１−ゲート開口部を形成する工程と、前記ノー
Ｉ−開［］部を含む全面に金属を被着した後バターニン
クＬノート開［−１部にゲート電極を形成する王稈とを
禽んで構成される。Means 1 for Solving Problems 1 The method for manufacturing a field effect transistor according to the present invention is to form a first semiconductor layer of high purity on a high resistance substrate, and then to form a first semiconductor layer-1 on the first semiconductor layer-1. One or more layers containing impurities of one conductivity type a) Second
a step of forming a conductor layer on the second semiconductor layer 1, a step of forming a mask having openings for the source and F L-in regions in the second semiconductor layer, and a step of forming a mask having an opening for the source and F L-in regions in the second semiconductor layer; Etching the semiconductor layer of 2 1. a step of exposing the first l'-conductor layer, and forming a high-concentration impurity layer of one conductivity type that is thicker than the mask and will serve as a source and tosine region on the exposed first semiconductor layer in the vertical IJ direction. After depositing an insulating film on the upper and the entire surface, this insulating film is etched using a front-back etching method, leaving the insulating film only on the sides of the high concentration impurity layer 1-, I culm, and the second Removal of the mask on the semiconductor layer 1 - Step of forming a gate opening, and after depositing metal on the entire surface including the open [] part, forming a gate electrode in the open [-1] part. It is composed of king culm and chicken.
［実施例′１
−．５−
次に、本発明の実施例について１゛ヌ１を参１１ｉ’（
１，’（説明する。[Example '1-. 5-Next, regarding the embodiments of the present invention, refer to 1.1 and 11i' (
1,'(Explain.
第１ Ｎ （ａ ）〜（ｉ＞は本発明の一実ｈｆｋ、例
を説明する為の一１程１１１０に示した半導体−ｆ−・
ツブ（１月１「而［７１である。1st N(a)~(i> is one of the embodiments of the present invention hfk, and the semiconductor -f-・ shown in 1110 for explaining an example
Tsubu (January 1, ``71.
まず第１図（ａ ＞に示ず、Ｌうに、高抵抗のＧａＡｓ
基板５十に分子線エピタキシ法によりＡ−ヤリア密度約
Ｉ Ｘ Ｉ Ｄ ”１ｌＡｌｚ・（ｍ’ 、厚さｌ Ｂ
ｍの１）型１ｉ ａ Ａ ｓからなる第１の半導ｔ４
層４を形成する。続いてこの−１−に厚さ２０人のアン
′ｌ・−ブ人１ ｎ 、 ３Ｇ ａ ａ 、 ７＾Ｓ層
、厚さ１００人（７）ｎ型 Ａｆｆ １１１ａａＯ，７
人５ｊｆ４．厚さ２００人の［１型Ａｅ ｘＧａ １Ｘ
ＡＳ層（Ｘは１１．３がｒ’）ｎｌ又と変化している）
及び厚さ２０ｒ１人の１１型ｌｉ ａ Ａ ｓ層がｔ）
なる第２の半導体層２を形成する。次に全面に厚さ３０
０（１）人のＳｉＯ□膜を形成し、 ｆ、後バター：ユ
ンクし、Ｆト−ｒ’の電流方向が＜ ０１．１ ＞にな
る、１うにソース及びＩ〜レイン領域の開ｒ−］部１ｏ
を１１．Ｑ７ｚＨ＋隔てて形成したマスク１を形成する
、次に、第１図（ｂ）に示すように、マスク１グ）開口
部１０にお（゛する第２の半導体層２と、第１の゛１′
、導体層４の上部をエツーＪンクする。First, in Figure 1 (a), a high-resistance GaAs
The molecular beam epitaxy method is applied to the substrate 50 to give an A-layer density of about I
1) First semiconductor t4 consisting of type 1i a A s of m
Form layer 4. Next, on this -1-, there is a layer of 20 people thick, 1 n, 3G aa, 7^S layer, 100 people thick (7) n type Aff 111aaO, 7
person5jf4. Thickness of 200 people [Type 1 Ae xGa 1X
AS layer (X changes from 11.3 to r') nl again)
and 11 type li a s layer with thickness 20 r)
A second semiconductor layer 2 is formed. Next, the thickness is 30 mm on the entire surface.
0(1) SiO□ film is formed, after f, the current direction of F to r' becomes < 01.1 >, 1 open r of the source and I to rain regions. ] Part 1o
11. Next, as shown in FIG. 1(b), a second semiconductor layer 2 is formed in the opening 10, and a first semiconductor layer 2 is formed in the opening 10, as shown in FIG. 1(b). ′
, the upper part of the conductor layer 4 is etched.
次に、第］ ＩＸｌ （＋・）に小ずように、開口部１
０（１４二お４−する第１の゛Ｖ導体層４上に水素化物
気相成長１人（１こ３１：す、１．（板ン晶Ｉ化６５０
°（、’、、て、キャリアン虚度６・・、１．０ ”
ｌ固′（■１、厚さ５ ｒｌ Ｏ０人のソース ）・ｌ
フィン領域となるＩｉ ’型ＧａＡｓＪｖ４６を成長さ
ｔ！−る。Next, open the opening 1 in a small way at No. IXl (+・).
Hydride vapor phase growth on the first V conductor layer 4 (1 31: 1.
°(,',,te,Carian vacancy 6...,1.0"
l solid' (■1, thickness 5 rl O0 sources)・l
Grow Ii' type GaAsJv46 which will become the fin region. -ru.
こ（１）ｒ１’ ４．１′！ＧａＡｓｒｌ ６はほぼ垂
直σ）側面を持−）で形成される。This (1) r1'4.1'! GaAsrl 6 is formed with approximately vertical σ) sides.
次に、第１図（ｄ）い示すように、スパッタ法に６１り
全面に厚さ約２ （’１００人の窒化シリ−１ン膜７を
形成する。Next, as shown in FIG. 1(d), a silicon nitride film 7 of about 200 m thick is formed over the entire surface by sputtering.
次（、二、第１図（（寸）に示すように、〔′Ｆ４カス
を用いるＷ方性Ｉ・ライエ・ソチンク法により窒化シリ
コ１シ１模７を工’ソチングし、丁１型ＧａＡｓ層００
）（同市１にａ）７ノ窒化シリ′：１シ１模７を残ず。Next (2) As shown in Figure 1 ((size)), silicon nitride 1 type 1 model 7 was processed by the W-oriented I-Rayet-Sochink method using F4 scraps, and 1-type GaAs Layer 00
) (In the same city 1 a) 7-nitride silicon': 1 shi 1 model 7 left.
この時、第１の゛１′、導体層・１１−の２次元電子チ
ャネル３の部分はマスク１により保護される為、素子特
性が劣化することはない９、
次に、第１図（＋’ ） ＋、、ｍ示ず、ｌ：う（、−
５）・ソ酸系溶渣に、Ｌ Ｑ ５ｉ０２１模からなるマ
スク１をｊ冗択的６゜：除去し、ゲート開１−１部２０
を形成する、次に、第１１図（ｇ＞に示す、Ｌ）に、全
面に１′）［さ５ Ｅｌ Ｏｆ〕人（７”） Ａｆｆ膜
８を形成し／ご後、バター二シグし、第１図（１１）に
小ずようにゲートｔｌｉ極８Ａを形成する。At this time, since the two-dimensional electron channel 3 portion of the first conductor layer 11- is protected by the mask 1, the device characteristics will not deteriorate9. ') +,,m not shown,l:U(,-
5) Remove the mask 1 made of L Q 5i021 from the soric acid solution by 6 degrees, and open the gate 1-1 part 20.
Then, on the entire surface as shown in FIG. , a gate tli electrode 8A is formed in a small manner as shown in FIG. 1 (11).
次に、第１図（ｉ）に示す、■、うに、＾ｕＧｅ音余及
びＮｉを被着した後バターＳユングと熱処理を行ない、
ｎ ”型ＧａＡｓ層６上にソース電極９ Ａ及びＦ ｌ
、イン電極Ｏ１３を形成する４、
この３１、うに本実施例においては、工・ソチンクし／
と第１の半導体層４上にソース・ｌ・１．イン領域とな
る１）゛型ＧａＡｓ層０を成長させる為に、シー１−
ｌｌＥ抗の小さなソース トドイン領域かｔ）られる。Next, as shown in Fig. 1(i), ■, sea urchin, ^uGe and Ni were coated, and then heat treated with butter S Jung.
Source electrodes 9A and F l are formed on the n'' type GaAs layer 6.
, to form the in-electrode O13.
and the source l.1 on the first semiconductor layer 4. In order to grow the 1) type GaAs layer 0, which will become the in region, the sea 1-
A small source of llE resistance is generated in the region.
又活性化の為の熱処理が小要な＆ｉｂ、第１ぴ）半導体
層４の結晶品質が低１・することはない。更に、ソース
及びトドイン領域であるｎ ”型ＧａＡｓ層６を設（′
）た後にデー１〜電極８Ａを自己整合て形成する為、ゲ
ート電極を形成する金属は耐熱性をイ」するものに限定
されない、従って、比抵抗σ）小さい金属かｔ、なるゲ
ート電極を有し、しかもノー１〜 ソース間及びゲート
トドイン間の耐圧のずり’ ｉ−＋たＦｌ尤′１゛を
製造することかできる。又従来のゲート電極に比べその
面積の小さなデー１〜電極を自己整合で形成できる為に
入力容量が小さくなり、Ｆ Ｅ Ｔの高速・高周波特性
は向１’、 Ｌ、、 ？＝ものとなる、尚、１■記実施
例では第２の半導体層としてｎ型ｆＮｉ物を含むＧａＡ
ｓ層等を用いｔ：場合について説明したが、［）型不純
物を含む１層以上の２１ソ導体層を用いても、上い。Further, the crystal quality of the first semiconductor layer 4, which requires no heat treatment for activation, will not deteriorate. Furthermore, an n'' type GaAs layer 6, which is a source and a todoin region, is provided ('
Since the electrodes 1 to 8A are formed by self-alignment after σ), the metal forming the gate electrode is not limited to a metal with high heat resistance. Moreover, it is possible to manufacture a Fl layer with a difference in breakdown voltage between the source and between the gate and the source. In addition, since the electrode with a smaller area than a conventional gate electrode can be formed by self-alignment, the input capacitance becomes smaller, and the high-speed and high-frequency characteristics of the FET are improved. In the embodiment described in 1.2, GaA containing an n-type fNi material is used as the second semiconductor layer.
Although the t: case has been described using an s layer or the like, it is also possible to use one or more 21 sol conductor layers containing [ ) type impurities.
１発明の効果］
ＤＪ、上説明したように本発明は、エッチングした第１
の半導体層トにソース・トレイン領域となる−・導電型
の高濃度不純物層を形成しｆ、：後に、この高濃度不純
物層と絶縁されたデー１〜電極を自己整合で形成するこ
とにより、デー１−抵抗が低くかつ短チャネル効用を起
すことのない微細な素子構造を有する電界効果１〜ラン
シスタを製造できる効果かある。1. Effects of the Invention] DJ, As explained above, the present invention has the advantage that the etched first
A high concentration impurity layer of conductivity type is formed in the semiconductor layer T, which will become a source/train region. Later, by forming electrodes insulated from this high concentration impurity layer in a self-aligned manner, Day 1 - Field effect 1 - Lancistor having low resistance and a fine device structure without causing short channel effects can be manufactured.
第１１Ｙｌ （ａ、 ） −（ｉ ）は本発明の一実施
例を説明する為の製造上稈順に小しＡ：半導体チップの
断面図、第２図は従来のＦ Ｆ、 Ｔ’ ＋７）製造方
法を説明する為の半導体チップの１（１１面図である。
■ ・マスク、２・第２の゛Ｖ導体層、３・２次九電子
チャネル、４・・・第１の半導体層、５・ｃ ａ Ａ
Ｓ −、Ｍ板、６− Ｎ＋型ＧａＡｓ層、７ 、、、
Ｑ化シリ′：１ン膜、８・・・Ａｆｆ膜、８Ａ・・デー
１〜電極、（＞Ａ・ソース電極、Ｃ）！ト・・トドイン
領域、１（）・・開［１部、１トアンＦ ’）”Ｇａ
Ａｓ層、１２−ｎ型 人ｐＧａＡｓ層、１３・＞’−１
・電極、２０ デし１〜開Ｌ１部。11th Yl (a, ) - (i) are small in order of manufacturing to explain one embodiment of the present invention A: sectional view of a semiconductor chip, FIG. 1 (11 side view) of a semiconductor chip for explaining the method. ■ Mask, 2 Second V conductor layer, 3 Second-order nine electron channel, 4 First semiconductor layer, 5・c a A
S-, M plate, 6- N+ type GaAs layer, 7,...
Q-Si': 1 film, 8...Aff film, 8A...day 1~electrode, (>A source electrode, C)! Todoin area, 1()...open [1 part, 1toanF')”Ga
As layer, 12-n type pGaAs layer, 13・>'-1
・Electrode, 20 mm 1~open L1 part.
Claims (1)
該第１の半導体層上に一導電型不純物を含む１層以上の
第２の半導体層を形成する工程と、該第２の半導体層上
にソース及びドレイン領域の開口部を有するマスクを形
成する工程と、前記開口部の第２の半導体層をエッチン
グし前記第１の半導体層を露出させる工程と、露出した
前記第１の半導体層上に前記マスクより厚くソース及び
ドレイン領域となる一導電型高濃度不純物層を垂直方向
に形成する工程と、全面に絶縁膜を被着した後異方性エ
ッチング法により該絶縁膜をエッチングし前記高濃度不
純物層の側面にのみに絶縁膜を残す工程と、前記第２の
半導体層上の前記マスクを除去しゲート開口部を形成す
る工程と、前記ゲート開口部を含む全面に金属を被着し
た後パターニングしゲート用開口部にゲート電極を形成
する工程とを含む事を特徴とする電界効果トランジスタ
の製造方法。forming one or more second semiconductor layers containing impurities of one conductivity type on the first semiconductor layer after forming a high-purity first semiconductor layer on a high-resistance substrate; forming a mask having openings for source and drain regions on the semiconductor layer; etching the second semiconductor layer in the openings to expose the first semiconductor layer; A step of vertically forming a highly concentrated impurity layer of one conductivity type that is thicker than the mask and serving as source and drain regions on the semiconductor layer, and etching the insulating film by an anisotropic etching method after depositing an insulating film on the entire surface. a step of leaving an insulating film only on the side surfaces of the high concentration impurity layer; a step of removing the mask on the second semiconductor layer to form a gate opening; and a step of forming a metal over the entire surface including the gate opening. A method for manufacturing a field effect transistor, comprising the step of patterning after deposition to form a gate electrode in a gate opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945286A JPS62177970A (en) | 1986-01-30 | 1986-01-30 | Manufacture of field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945286A JPS62177970A (en) | 1986-01-30 | 1986-01-30 | Manufacture of field-effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62177970A true JPS62177970A (en) | 1987-08-04 |
| JPH0523497B2 JPH0523497B2 (en) | 1993-04-02 |
Family
ID=11999708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1945286A Granted JPS62177970A (en) | 1986-01-30 | 1986-01-30 | Manufacture of field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62177970A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH038344A (en) * | 1989-06-06 | 1991-01-16 | Fujitsu Ltd | A method for manufacturing a semiconductor device and a semiconductor device manufactured thereby |
| JP2008223927A (en) * | 2007-03-14 | 2008-09-25 | Saginomiya Seisakusho Inc | Check valve |
| CN106057883A (en) * | 2016-07-18 | 2016-10-26 | 中国工程物理研究院电子工程研究所 | Manufacturing method of high electron mobility transistor |
| CN111415987A (en) * | 2020-04-09 | 2020-07-14 | 浙江大学 | Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof |
-
1986
- 1986-01-30 JP JP1945286A patent/JPS62177970A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH038344A (en) * | 1989-06-06 | 1991-01-16 | Fujitsu Ltd | A method for manufacturing a semiconductor device and a semiconductor device manufactured thereby |
| JP2008223927A (en) * | 2007-03-14 | 2008-09-25 | Saginomiya Seisakusho Inc | Check valve |
| CN106057883A (en) * | 2016-07-18 | 2016-10-26 | 中国工程物理研究院电子工程研究所 | Manufacturing method of high electron mobility transistor |
| CN111415987A (en) * | 2020-04-09 | 2020-07-14 | 浙江大学 | Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0523497B2 (en) | 1993-04-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |