JPS59172776A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a field effect transistor using a compound semiconductor.

(Prior art) Field effect transistor (hereinafter referred to as FE) using compound semiconductor
(referred to as T) has been attracting attention because of its excellent advantages such as high mobility and the ability to use a semi-insulating crystal substrate, which reduces stray capacitance.

FIG. 1 is a diagram showing a conventional island manufacturing process of an FET using GaAs as a compound semiconductor. First, in FIG. 1(a), by ion-implanting Sl into a semi-insulating GaAs substrate 1 using the -(turned turned SiO□ film 2 and resist film 3 as masks), the n source region 4 and the total drain region are Form region 5. In FIG. 1(b), 5i
After once removing the 021mata 2 and the resist film 3'ffi, a rotten 5iQ2 film 6 and a resist film 7 are formed on the entire surface and patterned as shown in the figure. Using this as a mask, St is ion-implanted to form the active layer 8. form.

Furthermore, the implanted Si is activated by annealing at a temperature of about 800°C. Finally, Figure 1 (c)
After removing the Si 02 film 6 and the Reminost film 7, a passivation film 9 is deposited on the entire surface, a part of which is removed, and a Schottky gate electrode 10, a source electrode 11, and a drain electrode 12 are formed in that part. do.

In such a manufacturing method, the length La of the active layer is a shot-crystal length La if mask alignment errors are taken into consideration.
A margin of about 1 μm on the left and right sides is required for the length Lg. However, in the case of compound semiconductors, the depletion layer 13 expands due to surface states in this margin, increasing channel resistance and hindering high speed performance.

(Object of the Invention) The present invention has been made in view of the above points, and an object thereof is to provide a method for manufacturing a semiconductor device that can realize a high-speed compound semiconductor FET with less influence of surface states.

(Example) The following is a second example of the method for manufacturing a semiconductor device of the present invention.
Explain by referring to the diagram. .

In FIG. 2(a), 21 is a semi-insulating GaAs substrate. First, St is ion-implanted into a selected surface portion of this substrate 21 using a patterned 5in2 film 22 and a resist group 23 as a mask. Especially n-type Ga
An As active layer 24 is formed. The carrier concentration of this active layer 24 is desirably about 1 to 2 X I 917 m-''.

Next, an n Ge layer 25 is formed on the active layer 24 as shown in FIG. 2(b). At this time, the nGe layer 25 and the active layer 24 are in ohmic connection. Note that the n Ge layer 2
Although the layer 5 may be polycrystalline, it is preferable to use an epitaxial layer because a lower ohmic resistance can be obtained.

Next, a resist 26 is deposited on the entire surface above the nGeGe layer 5 as shown in FIG. 2(C). Then, an opening 27 is formed in the resist 2G in the r-) electrode region. Thereafter, the nGe layer 25 in the opening 27 is selectively etched by plasma etching using CF4+02. At this time, as shown in FIG. 2(e), 0.1 to 0.
Etching is performed under conditions such that the side is etched by about 2 μm. When this etching is performed, the nGe layer 25 is separated into left and right sides, and the source electrode 25 and the drain electrode 25 .
becomes.

After that, Ti/Pt/A was applied with the resist 26 remaining.
u (Schottky dart electrode metal) is deposited on the entire surface. When this vapor deposition is performed, Schottky dart electrodes 28 are formed on the active layer 24 in the openings 27 of the resist 26 in correspondence with the openings 27.

Thereafter, the resist 26 is removed using a solvent or the like. As a result, the FET is completed as shown in FIG.

According to one embodiment as described above, the distance between the source and drain electrodes 25□252 is set to 0.1 to 0.2 μm by using the side etching of the nGe layer 25, and the self-line V
Schottky P-) electrode 28 can be manufactured from C. Then, the Schottky P-) 11' bipole 28 and the source/drain electrode 25. ．． 252 is close to each other at 0.2 μm or less, the influence of the depletion layer due to surface states can be reduced, and therefore, the channel resistance can be reduced and a high-speed FET can be realized.

In addition, the n+00 layer 25 and the n-GaAs layer (active layer 24
) No alloy layer is formed at the interface. therefore,
Schottky characteristics can be easily obtained by forming a Schottky electrode 28 on the surface of the active layer 24 from which the n+00 layer 25 has been removed.

In the above embodiment, the source/drain electrodes 25 are formed on the active layer 24 in the process shown in FIG.
As a semiconductor layer that becomes 1,252 (ohmic electrode),
Although highly doped n-type r-rumanium is used, other materials such as heavily doped n-type silicon or InGaAs may also be used. That is, the semiconductor layer is
Any semiconductor material that has a /6 band width smaller than GaAs and is highly doped to n-type may be used.

(Effects of the Invention) As detailed above, the method for manufacturing a semiconductor device of the present invention allows the gate electrode and the source/drain/electrode to be formed close to each other, thereby producing a high-speed FET with less influence of surface states. In addition, the Schottky characteristics of a solid electrode can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a conventional manufacturing process of an FET using GaAs as a compound semiconductor, and the second figure is a cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention. 21... Semi-insulating GaAs substrate, 24... N-type G
aAs active layer, 25-nGe layer, 25. , 25.・・・
・Source/drain electrode, 26...resost, 27・
...Aperture, 28...Schottky gate electrode. Patent applicant Oki Electric Industry Co., Ltd. Figure 1

Claims (1)

[Claims] n-type QaA on selected surfaces of a semi-insulating GaAs substrate.
A step of forming an s-active layer, a step of depositing a semiconductor layer having a narrower band width than the above-mentioned GaAs which is highly doped to n-type on the active layer, and applying a resist to the entire surface including the semiconductor layer and the top thereof. forming an opening in the resist in the dirt electrode region, using the opening to side-etch and remove the semiconducting layer in the opening, and then removing the electrode metal. evaporated,
A method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode on the active layer in the opening, and then removing the resist.