JPS62165356A - Complementary insulated gate field effect transistor and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To readily obtain a fine CMOS adapted for a high integration by forming both N-channel and P-channel gate electrodes in one groove. CONSTITUTION:A silicon dioxide film 26 and a silicon substrate 21 epitaxial layer 25 are etched to form grooves A31, B32, N-type impurity ions are implanted by an ion implanting method on the surface of the substrate 21 and the bottom of the groove A31 to form N<+> type diffused layers 35, 36. P-type impurity ions are implanted to the surface of the layer 25 and the bottom of the groove B32 to form P<+> type diffused layers 38, 39. A silicon dioxide film 24' is etched by an RIE technique to the bottoms of the grooves A31, B32. A polycrystalline silicon is etched to allow the polycrystalline silicon to remain only on the side walls of the grooves A31, B32 as gate electrodes 44, and the electrodes 44 are thereafter oxidized by a thermally oxidizing method. After the silicon dioxide films of the bottoms of the grooves A31, B32 are removed by etching, a conductive substance 46 is deposited to bury the grooves A31, B32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary insulated gate field effect transistor formed using a trench and a method for manufacturing the same.

[Conventional technology]

Complementary insulated gate field effect transistor (CMO8)
) has the advantages of low power consumption and high noise margin, and its field of use is currently rapidly expanding. However, since the CMOS has a deep well region 52 as shown in FIG. 3, a wide isolation region 53 is required, which makes it difficult to miniaturize the CMOS and becomes a major problem when achieving high integration.

Conventionally, various methods have been attempted to achieve high integration of CMOS. For example, the International Solid State Devices Conference (In
international Electron 1lev
ices Meeting) 1982, 237-2
Dee 1 Trench Isolated on page 40
Seamos Devices (DI!HP TRENCII
l5OLATli:It CMOS DEVICES)
In a paper published under the title, a trench was formed to isolate the deep well region as shown in FIG. 4, and the trench was filled with a silicon dioxide film 63, 65 and polycrystalline silicon 64 to form an isolation region. , one in which the separation region width is miniaturized is shown.

[Problem that the invention seeks to solve]

However, in order to further miniaturize a CMOS which has been miniaturized by providing grooves in this manner, the gate electrode formed on the silicon substrate must be miniaturized. However, when the gate electrode is made finer, the channel length becomes shorter and the short channel effect becomes more pronounced.

An object of the present invention is to eliminate such conventional problems and provide a fine CMOS suitable for high integration and a manufacturing method thereof.

Means for Solving Problems] 5. The complementary insulating gate field effect transistor of the first aspect of the present invention has a first conductivity type semiconductor substrate formed in a first conductive type semiconductor substrate. an isolation region formed by an insulating film embedded in a second trench provided in the first trench; A first groove is formed on one of the first conductivity type semiconductor substrates separated by the second #4 so that the depth of the junction with the first conductivity type semiconductor substrate is shallower than the depth of the second groove. a second conductivity type impurity layer, a gate insulating film formed on a side wall of the first conductivity type semiconductor substrate in the first groove and the opposite side wall thereof, a second conductivity type of the first conductivity type semiconductor substrate and the first second conductivity type semiconductor substrate; The type impurity layer refers to the gate electrode formed along the first trench sidewall so as to be in contact with each other through the gate insulating film, and the first conductivity type semiconductor at the bottom of the first trench separated by the second trench. a second second conductivity type impurity layer formed on the substrate side and a first first conductivity type impurity layer formed on the other first second conductivity type impurity layer side; a third second conductivity type impurity layer formed on the surface of the first conductivity type semiconductor substrate separated by the second groove so that an end thereof is in contact with the gate insulating film; A second first conductivity type impurity layer formed on the surface of the first first conductivity type impurity J- separated in the second step so that an end thereof is in contact with the insulation film; an insulating film formed to cover the electrode surface;
The second second conductivity type impurity layer and the first first conductivity type impurity layer formed at the bottom of the groove are in contact with each other at the bottom of the first groove, and an electrode is formed to fill the first hot water. Consists of ages.

Further, the complementary insulated gate field effect i of the second invention of the present invention
41-L>' Sister manufacturing method includes the steps of providing a first groove on a first conductivity type semiconductor substrate, covering the sidewalls of the first groove with an insulating film, and covering the groove with a first conductivity type semiconductor substrate. (5) forming a second conductive type pure layer in the first conductive type semiconductor so that the insulating film is shallow; Semiconductor substrate and Mj
The insulating film is formed on the semiconductor of the first conductivity type, and the second impurity layer is shallower than the second impurity layer of the first conductivity type. a step of forming a third groove, a step of forming a second conductivity type impurity layer on the surface of the first conductivity type semiconductor substrate and a bottom of the second groove; Said third
forming a first conductivity type impurity layer at the bottom of each groove;
The insulating film is removed from the second insulating film. 3rd) Etch to the depth of the groove and 2nd. forming a fourth groove including a third groove; forming a gate insulating film and a gate electrode on the sidewalls of the fourth groove; and covering the surface of the gate electrode with an insulating film material; Said 2nd. forming a conductive material so as to connect to the first and second conductivity type impurity layers formed at the bottom of the third trench through the bottom of the third trench, and to fill the 71st trench. .

[Example〕 Hereinafter, embodiments of the present invention will be described using the drawings.

FIG. 1 shows a schematic cross-sectional view of one embodiment of the present invention, and FIGS. 2(a) to (1) show the steps in the order of steps for explaining the manufacturing method of one embodiment of the present invention. FIG.

In FIG. 1, gate insulating films 2 and 3 of CMOS n-channel + p-channel and electrodes 4,
5 are formed along the side walls of the trenches, and the well regions 10 are separated by an insulating film 11 buried in the trenches.

The drain and source of the n-channel and n-channel are respectively the p-type silicon plate 1 surface J3 and the n1 diffusion layer 6 at the bottom of the pot.
8. It is formed by a p+ diffusion layer 7°9. C.M.O.
The output electrode of S is the bottom of the n1 diffusion layer 6 and the p+ diffusion layer 9.
The conductive material is connected to the groove and filled in the groove.

Next, the manufacturing force method of the embodiment will be explained with reference to FIGS. 2(a) to 2(1).

First, as shown in FIG. 2(a), a p-type silicon single crystal substrate 21. -, I= silicon dioxide film 2 by thermal oxidation method
2 is formed, and then the area other than the vortex forming area is covered with a resist 23.

Next, as shown in FIG. 2(b), reactive ion etching (RIIE',
) technique to remove the silicon dioxide film 22 and the silicon substrate 21 to form grooves, and then a thick silicon dioxide film 24 is deposited over the entire surface by the CVD method.

Next, as shown in FIG. 2(c), the silicon dioxide film 24 is etched using the R, IF, technique to leave the silicon dioxide film 24' only on the side walls of the trench, and then the silicon dioxide film 24' is etched using the selective epitaxial growth technique. Only on the surface of the substrate is a layer of crystalline silicon of the same conductivity type as the silicon substrate 21 (epitaxial A/
A silicon dioxide film 26 is grown to fill the trench, and the surface of the epitaxial layer 25 is coated with a silicon dioxide film 26 by thermal oxidation.

Next, as shown in FIG. 2(d), an epitaxial layer 2 is formed.
The regions other than 5 are covered with a resist 27, and then an n-type impurity is implanted into the surface of the epitaxial layer 25 using the resist 27 as a mask by ion implantation to form an n-type impurity layer 28.

Next, as shown in FIG. 2(e), the resists 1 to 27 are removed, and then high-temperature heat treatment is performed to push the n-type impurity of the impurity layer 28 into the epitaxial layer 25 to form an n-well region 29. After that, the area other than the area where the silicon dioxide film 24' is formed and its surrounding area = 10- is covered with a resist 30, and then the silicon dioxide film 26 and the silicon substrate 21 epitaxial layer 25 are etched using the TE technique. Form A31°B32. In addition, Lecture A31. B32 is formed shallower than the n-well region 29.

Next, as shown in FIG. 2(f), after removing the resist 30, the vortex A31. ．． A thin silicon dioxide film 33 is formed on the inner wall of B32, and the epitaxial layer 25 and the surface of layer 832 are covered with resist I.34, and then the surface of silicon substrate 21 and layer A are coated by ion implantation.
N-type impurities are implanted into the bottom of each layer 31 to form an n+ diffusion layer 35.
．． form 36.

Next, as shown in FIG. 2 (g), after removing the resists 1 to 34, the silicon substrate surface 21 and the surface of the vortex A 31 are covered with a resist 37, and then the surface of the epitaxial layer 25 is formed by ion implantation. Then, n-type impurities are implanted into the bottom of layer B32 to form p+ diffusion layers 38 and 39.

Next, as shown in FIG. 2(h), after a resist 40 is applied to the entire surface, an insulating coating material 41 is applied to the entire surface, and then the resist is applied except for the silicon dioxide film 24' area and its surrounding area. Apply 42.

Next, as shown in FIG. 2 (i>), the insulating coating material 41 is etched using the R, IE technique using the resist l-42 as a mask, and then RIE is performed using the insulating coating material 41 as a mask. The resist 40 is etched to the surface of the silicon dioxide film 24' using a technique, and then the silicon dioxide film 24' is etched by R.
, groove A31. using IE technique. Etch to the bottom of B32.

Next, as shown in FIG. 2(, j), the resist l-40 and the silicon dioxide film 33 are each removed, and then the trenches A31. After forming a gate oxide film 43 on the inner wall of B32, low-resistance polycrystalline silicon is deposited on the entire surface using the CVD method, and then the polycrystalline silicon is etched using RTE technology to form the trench A31. The polycrystalline silicon is left only on the side walls of B32 to form a gate electrode 44, and then the gate electrode 44 is oxidized by a thermal oxidation method to form a silicon dioxide film 45 on its surface.

Next, as shown in section 21'4 (k >, the silicon dioxide film at the bottom of B32 is etched away using the RfE technique, and then a conductive material 46 is deposited to form the layer A3). , B32. Examples of the conductive material 46 include tungsten, molybdenum, titanium, etc., and methods for depositing it include CV D, sputter deposition, and bias sputtering.

rEffects of the Invention] According to the present invention, both the n-channel and p-channel gate electrodes are formed in one circuit, so compared to the conventional CMOS structure in which the gate electrode is formed on the surface of the silicon substrate. It becomes possible to significantly reduce the surface area. Furthermore, the lengths of both the n-channel and p-channel are determined by the depths of A and B. Therefore, there is an advantage that there is no need to worry about the short channel effect by ensuring a sufficient depth of the groove even in a fine MOS.

As described above, according to the present invention, a fine CMO8 suitable for high integration and a method for manufacturing the same can be easily obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of one embodiment of the present invention, and FIG.
) to (1() are schematic sectional views shown in order of steps to explain the manufacturing method of one embodiment of the present invention, and FIG. 3 is a conventional C
A schematic cross-sectional view of an example of MO8, Figure 4 is a conventional CMO8
FIG. 2 is a schematic cross-sectional view of a groove type separation structure in FIG.

Claims (2)

[Claims] (1) An isolation region formed by an insulating film embedded in a second trench provided in the bottom center of the first trench provided in the first conductivity type semiconductor substrate, and the first and second trenches. a first second conductivity type impurity formed on one of the separated first conductivity type semiconductor substrates so that the depth of the junction with the first conductivity type semiconductor substrate is shallower than the depth of the second groove; layer, a gate insulating film formed on a side wall of a first conductive type semiconductor substrate in the first groove and its opposing side wall, and the first conductive type semiconductor substrate and the first second conductive type impurity layer. A gate electrode formed along the first trench sidewall so as to be in contact with the first trench sidewall through the gate insulating film and at the first trench bottom with an insulating film in between; A second second conductivity type impurity layer formed on the first conductivity type semiconductor substrate side of the first groove bottom separated by a third second conductivity type impurity layer formed on the surface of the first conductivity type semiconductor substrate separated by the first and second grooves so that an end thereof is in contact with the gate insulating film; a second first conductivity type impurity layer formed on the surface of the first second conductivity type impurity layer separated by the impurity layer and the first and second grooves so that an end thereof is in contact with the gate insulating film; an insulating film formed to cover the surface of the gate electrode; a second impurity layer of a second conductivity type formed at the bottom of the first groove and in contact with the gate electrode through the insulating film; A complementary insulated gate field effect transistor characterized in that the first conductivity type impurity layer of No. 1 includes an electrode formed in contact with a part of the bottom of the first trench and further filling the first trench. (2) a step of providing a first groove on a first conductivity type semiconductor substrate and covering the sidewall of the first groove with an insulating film; a step of filling the groove with a first conductivity type semiconductor; forming a second conductivity type impurity layer in the conductivity type semiconductor so as to be shallower than the insulating film; and forming a second conductivity type impurity layer on the first conductivity type semiconductor substrate and the first conductivity type semiconductor sandwiching the insulating film. forming second and third trenches shallower than the insulating film and the second conductivity type impurity layer; a step of forming an impurity layer, a step of forming a first conductivity type impurity layer on the surface of the first conductivity type semiconductor and a bottom of the third groove; A step of etching to a depth to form a fourth trench including the second and third trenches, a step of forming a gate insulating film and a gate electrode on the side walls of the fourth trench, and a step of etching the surface of the gate electrode with an insulating film. a conductive material so as to connect to the first and second conductivity type impurity layers formed at the bottoms of the grooves through the bottoms of the second and third grooves and to fill the fourth groove; 1. A method of manufacturing a complementary insulated gate field effect transistor, the method comprising: forming a complementary insulated gate field effect transistor.