KR940011096B1 - Device for isolation of semiconductor apparatus - Google Patents

Abstract

The method includes the steps of sequentially forming a first oxide film, a nitride film and a second oxide film on a semiconductor substrate, applying a mask onto the second oxide film to define device isolation and formation regions to form an opening part (OP), forming a channel stop layer into the substrate through the opening part, forming a spacer (11) on the inner wall of the opening part to etch the substrate to form a trench (20), thermal-growing an oxide film onto the inner part of the trench to form a third oxide film, and forming an insulating layer onto the trench, thereby minimizing the size of device isolation region and reducing a narrow channel effect.

Description

Device Separation Method of Semiconductor Device

1A to 1E are process flow charts showing a process of forming a device isolation region using a conventional trench.

2 is a longitudinal cross-sectional view of a transistor formed by applying a conventional device isolation technique.

3A to 3F are process flow diagrams of an embodiment showing a process of forming a device isolation region according to the present invention.

4 is a longitudinal sectional view of a transistor formed by applying the device isolation technique of the present invention.

* Explanation of symbols for main parts of the drawings

10a: channel stop layer 10b: channel stop layer

11 spacer 20 trench

100 semiconductor substrate N nitride film

OP: openings OX1, OX2, OX3, OX4: 1st, 2nd, 3rd, 4th oxide film

The present invention relates to a device isolation method of a semiconductor device, and more particularly to a device isolation method of a semiconductor device that can minimize the device isolation region.

Recently, as the development of semiconductor manufacturing technology and the application fields of memory devices are expanded, the development of large-capacity memory devices is progressing, and the capacity of such memory devices is based on micro process technology, which is doubled for each generation. It has been promoted by research. In particular, the reduction of the device isolation region separating the devices is one of the important items in the miniaturization technology of the memory device.

In the device isolation technology, a LOCOS (LOCal Oxidation of Silicon) used to selectively grow a thick oxide film on a semiconductor substrate to be used as a separation region, and a semiconductor substrate in the isolation region are etched, and a nitride film is formed on the side surface to remove from the isolation region during field oxidation. Side WAll Masked Isolation (SWAMT), which prevents the formation of an oxide film in the device formation region, SEPOX (Secure Polysilicon Oxidation) used as an isolation region by oxidizing a polysilicon film, and a BOX (Buried OXide isolation) that fills an insulator by forming a groove Etc. can be mentioned.

1A to 1E are process steps showing the formation and fixing of device isolation regions using conventional trenches.

FIG. 1A illustrates a process of forming the opening OP. First, the first oxide film OX1, the nitride film N, and the second oxide film OX2 are formed on the first conductive semiconductor substrate 100. Form in turn. In order to expose the semiconductor substrate corresponding to the isolation region, an opening OP is formed by sequentially etching the second oxide film, the nitride film, and the first oxide film by applying a photoresist pattern on the second oxide film. .

FIG. 1B illustrates a process of forming the trench 20 and the channel stop layer 10b. The trench 20 having a predetermined depth is formed in the semiconductor substrate corresponding to the isolation region exposed through the opening, and the field inversion is prevented. The channel stop layer 10b is formed by injecting oblique ions into the first conductive type impurity. In addition, a third oxide layer OX3 is formed on the inner surface of the trench 20 to remove defects that occur in the semiconductor substrate when the trench 20 is formed.

FIG. 1C illustrates a process of forming an insulator, such as a fourth oxide layer OX4, to fill the trench 20 after the process of FIG. 1B to sufficiently fill the trench.

FIG. 1D illustrates a process of leaving the fourth oxide layer OX4 only in the trench 20 through an etchback process using the nitride layer N as an etch stop layer after the process of FIG. 1C.

The device isolation process is completed by sequentially removing the nitride film and the first oxide film after the process of FIG. 1E or 1D.

In the conventional device isolation method using a trench, a device isolation process is completed by forming a trench in a semiconductor substrate corresponding to an isolation region and filling an oxide film in the trench. In this case, an oxide film is formed on the inner surface of the trench to remove defects generated in the semiconductor substrate when the trench is formed. At this time, a brid's beak is formed from the edge of the trench inlet toward the device forming region. This buzz beak is etched when the oxide film is formed to fill the trench, and is then etched to complete the final device isolation process. Thus, as shown in FIG. 1e, a bent portion is formed on the surface of the semiconductor substrate adjacent to the upper portion of the trench. To me. Therefore, referring to FIG. 2 showing a result of fabricating a transistor by applying the above-described conventional device isolation technique, as shown in FIG. Areas that are vulnerable to injection are formed. As a result, when a voltage is applied to the gate electrode 31, an inversion layer is easily formed in the region 33 where the ion implantation is vulnerable, thereby forming a parasitic leakage current path so that a double hump is formed on the sub-threshold curve. Phenomena will appear. Here, reference numeral 30 in FIG. 2 denotes a gate oxide film.

Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device capable of improving the characteristics of the device isolation region in order to solve the problems of the prior art as described above.

In order to achieve the above object, the method of the present invention comprises the steps of sequentially forming a first oxide film, a nitride film and a second oxide film on a semiconductor substrate of a first conductivity type, and applying and removing a device formation region and isolation by applying a mask on the second oxide film. Forming an opening to expose the substrate on the peninsula corresponding to the separation region after defining the region, forming a channel stop layer on the semiconductor substrate exposed through the opening, and after forming the channel stop layer, And forming a spacer on an inner wall of the opening, and forming an insulator in the trench and in the periphery of the trench inlet.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

3A to 3F are process flowcharts of an embodiment showing a process of forming a device isolation region according to the present invention.

FIG. 3A shows a process of forming the opening OP and the channel stop layer 10a. First, a first oxide film having a thickness of about 100 GPa to 500 GPa, referred to as a buffer oxide film, is formed on a first conductive type, for example, a P-type semiconductor substrate 100. FIG. (OX1) is thermally grown, and a nitride film (N) of about 1000 kPa to 3000 kPa is formed on the first oxide film (OX1) by LPCVD (Low Pressure Chemical Vapor Doposition) method, and about 1000 kPa to 5000 kPa on nitride film (N). The second oxide film OX2 is formed by the CVD method. In order to define a device formation region and a separation region by applying a photoresist pattern on the second oxide layer and to expose the semiconductor substrate corresponding to the separation region, the second oxide layer, the nitride layer, and the first oxide layer are sequentially etched. As shown, the opening OP is formed. Subsequently, the channel stop layer 10a is formed by ion implantation of impurities of a first conductivity type, for example, boron, to prevent field reversal.

FIG. 3B illustrates a process of forming the spacer 11. After the process of FIG. 3A, an oxide film is formed on the entire surface by thermal oxidation or CVD and then anisotropically etched the oxide film by dry etching. The spacer 11 is formed on the inner wall of the opening.

3C illustrates the process of forming the trench 20. The trench 20 is formed by etching the semiconductor substrate exposed after the spacer 11 is formed to a predetermined depth. Here, the channel stop layer may be formed once more as shown by reference numeral 10b to adjust the device characteristics of the device formation region.

FIG. 3D illustrates a process of forming the third oxide film OX3 and the fourth oxide film OX4. The third oxide film OX3 may be formed on the inner surface of the trench 20 to remove defects generated in the semiconductor substrate when the trench 20 is formed. 3 The oxide film OX3 is thermally grown. In addition, an insulator for filling the trench 20, for example, a fourth oxide layer OX4, is deposited thickly by CVD to sufficiently fill the trench.

FIG. 3E or 3D shows a process of leaving the fourth oxide layer OX4 in the trench 20 and in the periphery of the trench inlet through an etch back process using the nitride layer N as an etch stop layer. Indicates. Accordingly, the device isolation region according to the present invention includes a fourth oxide film formed in the trench and a periphery of the trench inlet, a third oxide film formed in FIG. 3d, and a spacer formed in FIG. 3b, that is, the trench inlet. Is formed of an oxide film extending laterally by a predetermined length. Thus, the edge portion of the trench inlet does not directly contact the device formation region. Here, the etching degree of the etch back process may be adjusted to adjust the thickness of the fourth oxide layer on the semiconductor substrate.

After the process of FIG. 3f or 3e is completed, the device isolation process is completed by sequentially removing the nitride film and the first oxide film.

As described above, although the P-type semiconductor substrate is used in the embodiment of the present invention, the N-type semiconductor substrate may be used.

As described above, in the present invention, the spacer is formed before the trench is formed, thereby removing the buzz beak phenomenon occurring at the edge of the trench inlet when an oxide film is formed on the inner surface of the trench to remove defects in the semiconductor substrate. I can eliminate it. Therefore, referring to FIG. 4 showing a result of fabricating a transistor by applying the device isolation technology of the present invention, as shown in reference numeral 35, the edge portion of the trench inlet is not directly in contact with the device formation region. There is no inversion layer, which eliminates the double hump phenomenon that appears on the sub-threshold curve. In addition, it is possible to minimize the device isolation region.

In addition, since trenches are formed after spacer formation, process margins such as ion implantation and oxide film formation for removing defects generated in the semiconductor substrate during trench formation can be sufficiently secured.

In addition, a narrow channel effect may be reduced by adjusting an impurity implantation process for forming a channel stop layer.

Therefore, the present invention is expected to be applicable to device isolation technology of 0.3 ㎛ ~ 0.4 ㎛.

Claims (4)

A step of sequentially forming a first oxide film, a nitride film, and a second oxide film on the first conductive semiconductor substrate; Forming an opening to expose a semiconductor substrate corresponding to the isolation region after defining a device formation region and an isolation region by applying a mask on the second oxide film; Forming a channel stop layer on the semiconductor substrate exposed through the opening; Forming a spacer on an inner wall of the opening after forming the channel stop layer; Forming a trench by etching the exposed semiconductor substrate to a predetermined depth after the spacers are formed; Thermally growing an oxide film on an inner surface of the trench to form a third oxide film; And forming an insulator in the trench and at the periphery of the trench inlet. 2. The device of claim 1, further comprising forming a channel stop layer by inclining ion implantation of impurities of a first conductivity type to prevent field reversal on the trench sidewalls after the trench is formed. Way. The method of claim 1, wherein the spacer is an oxide film. The method of claim 3, wherein the oxide spacer is formed by growing an oxide film on the semiconductor substrate exposed through the second oxide film and the opening by chemical vapor deposition, and then anisotropically etching the oxide film through a dry etching method. A device isolation method for a semiconductor device.