JPS6188529A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6188529A JPS6188529A JP21070584A JP21070584A JPS6188529A JP S6188529 A JPS6188529 A JP S6188529A JP 21070584 A JP21070584 A JP 21070584A JP 21070584 A JP21070584 A JP 21070584A JP S6188529 A JPS6188529 A JP S6188529A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- cms
- fine
- layer
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体基板
上の段部の平坦化方法と微細パターン形成方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for flattening a stepped portion on a semiconductor substrate and a method for forming a fine pattern.
複数の素子領域が形成された半導体基板上は、素子領域
を形成するための絶縁層や素子領域から導出された導体
層のために複数の段部を有し、レジストでの微細パター
ン形成にはきわめて不利である。−万、微細加工におい
ては、リアクティブイオンエツチング(以下AIDと略
す)が主流であ)、耐ドライエツチング性の良好なレジ
ストが求められているが、現状では、工程によ923m
以上の厚いアジド系紫外線レジストヲ使用し、ウェット
現像するしかなく微細パターン形成には。A semiconductor substrate on which a plurality of element regions are formed has a plurality of steps for an insulating layer for forming the element regions and a conductor layer led out from the element regions. This is extremely disadvantageous. - In microfabrication, reactive ion etching (hereinafter abbreviated as AID) is the mainstream), and a resist with good dry etching resistance is required.
The only way to form fine patterns is to use thick azide-based UV resists and wet develop them.
限界がある。There is a limit.
また、几IEにおける微細加工においては、レジストの
形状が影響をおよぼすため従来のウェット現像では、垂
直な形状は得られに<<、ドライエツチングによる加工
を行う必要がある。Furthermore, since the shape of the resist affects microfabrication in IE, a vertical shape cannot be obtained by conventional wet development, and processing by dry etching is required.
以上の点を解決するため、多層レジスト法が考えられて
いる。従来の多層レジストは、中間層のある三層レジス
ト法によるものがほとんどである。In order to solve the above points, a multilayer resist method has been considered. Most conventional multilayer resists are based on a three-layer resist method with an intermediate layer.
これは、工程的にも複雑であシ、02プラズマを使用し
、1層目レジストをパターニングするため垂直なレジス
ト形状が得られにくいという問題がある。This method is complicated in terms of process, and since 02 plasma is used to pattern the first resist layer, there is a problem in that it is difficult to obtain a vertical resist shape.
そこで、本発明によれば、CF4プラズマに対して、耐
ドライエツチ性がないが、塩素系ガスプラズマには、大
きな耐ドライエツチ性を有するクロロメチルスチレン(
以下CM8と略す)を基礎としたディープウルトラバイ
オレットレジストを1層目に使用し、CF4に対して耐
ドライエツチ性の大きいアジド系の紫外線レジストを2
層目に使用することKよってCF、の几IEで1層目の
CMSをパターニングすることを特徴とする2層レジス
ト法を提供するものである。Therefore, according to the present invention, chloromethylstyrene (which has no dry etch resistance against CF4 plasma but has high dry etch resistance against chlorine gas plasma)
A deep ultra violet resist based on CM8 (hereinafter abbreviated as CM8) is used as the first layer, and an azide-based UV resist with high dry etch resistance against CF4 is used as the second layer.
This invention provides a two-layer resist method characterized in that the first layer CMS is patterned using a CF IE for the first layer.
以下1図面を参照して、本発明の実施例を示す。 Embodiments of the present invention will be described below with reference to one drawing.
第1図にその工程を示すように、All上KCM8レジ
スト2を2〜3μm塗布し、ベークして固める(図囚)
。これにより、Aeの段差によるレジストの凸凹をやわ
らげることができる。CMSレジスト2は第2図に示す
ように、耐ドライエツチング性はないが、塩素系ガスプ
ラズマには大きな耐ドライエツチング性を示す。その後
アジド系紫外線レジメ)ecMsレジスト2の3分の工
程度塗布し、蕗光し、ウェット現像を行う(第1図(均
)。アジド系の紫外線レジスト2は、第2図に示すよう
に、CF4に対する耐ドライエツチング性が大きい。次
に2層目のレジストを塗布し露光するが、その時、下地
は平坦であり、反射などもないので2層目のレジストの
fil+パターン形成はきわめて有利である。次にCF
、ガスを用いたR、IEでCM8レジストをドライ加工
する(第1図(q)。几IEを使うことで微細なレジス
トパターンが垂直な形状でできあがる。この様に従来問
題となった。#細化に不利な段差、レジストの厚さが、
この方法で解決され、1μm以下の微細なパターンが形
成できる。As shown in Fig. 1, KCM8 resist 2 is applied to the All surface to a thickness of 2 to 3 μm and baked to harden it (see figure).
. This makes it possible to soften the unevenness of the resist due to the step difference in Ae. As shown in FIG. 2, the CMS resist 2 has no dry etching resistance, but exhibits high dry etching resistance against chlorine gas plasma. After that, azide-based ultraviolet ray resist 2) is applied in a 3-minute step, exposed, and wet developed (Fig. 1 (uniform).Azide-based ultraviolet ray resist 2 is applied as shown in Fig. 2. High dry etching resistance against CF4.Next, the second layer of resist is applied and exposed, but at that time, the base is flat and there is no reflection, so forming a fil+pattern of the second layer of resist is extremely advantageous. .Next, CF
CM8 resist is dry-processed using R and IE using gas (Fig. 1 (q)). By using IE, a fine resist pattern can be created in a vertical shape. This has been a problem in the past. # Steps and resist thickness are disadvantageous to thinning.
This method solves the problem and allows formation of fine patterns of 1 μm or less.
本実施例では、Aeのパターニングについて行っている
が、特に塩素系ガスを用いる几IEにおいて適用できる
ものである。このCMSというレジストは、塩素系のガ
スでの几IEに対しては。In this embodiment, Ae patterning is performed, but it is particularly applicable to IE using chlorine-based gas. This resist called CMS is effective against IE using chlorine-based gas.
特に良好な耐ドライエツチ性を示すので、Ae。Ae because it shows particularly good dry etch resistance.
ポリ−8iだけでなく、アイソレーションヲ行つ場合の
深いエツチングには有効な方法である。This method is effective not only for poly-8i but also for deep etching when performing isolation.
第1図四〜(qはAe工程へ本発明を適用した実施例を
工程類に示した断面図で、第2図は各レジストのエツチ
ングレートを示すグラフである。
1・・・・・・Ae、2・・・・・・0MSレジスト、
3・・・・・・アジド系レジスト、4・・・・・・CF
4 リアクティブ・イオン・エツチング、5・・・・・
・パターニングされりAe0
(Cツ
ヤ厘固1.4-(q is a sectional view showing the steps of an embodiment in which the present invention is applied to the Ae process, and FIG. 2 is a graph showing the etching rate of each resist. 1... Ae, 2...0MS resist,
3...Azide resist, 4...CF
4 Reactive ion etching, 5...
・Patterned Ae0 (C gloss hard
Claims (1)
基礎にしたディープウルトラバイオレットレジストを使
用し、2層目として薄いアジド系の紫外線レジストを使
用する工程と、前記2層目のレジストをマスクとして、
CF_4系ガスを用いたリアクティブイオンエッチング
で、前記1層目のパターニングを行う工程とを特徴とす
る半導体装置の製造方法。A step of using a thick chloromethylstyrene-based deep ultraviolet resist as a first layer on the semiconductor and a thin azide-based ultraviolet resist as a second layer, and using the second layer resist as a mask,
A method for manufacturing a semiconductor device, comprising the step of patterning the first layer by reactive ion etching using CF_4-based gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21070584A JPS6188529A (en) | 1984-10-08 | 1984-10-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21070584A JPS6188529A (en) | 1984-10-08 | 1984-10-08 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6188529A true JPS6188529A (en) | 1986-05-06 |
JPH0527969B2 JPH0527969B2 (en) | 1993-04-22 |
Family
ID=16593732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21070584A Granted JPS6188529A (en) | 1984-10-08 | 1984-10-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6188529A (en) |
-
1984
- 1984-10-08 JP JP21070584A patent/JPS6188529A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0527969B2 (en) | 1993-04-22 |
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