JPH04155816A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control resist pattern in a highly precise manner by a method wherein the resist of lower layer is removed by O2 plasma, an oxide layer is formed on an etching film, and it is used as a mask. CONSTITUTION:An SiO2 film 1 and a polysilicon film 2 are formed on a semiconductor substrate, a resist 3 is applied thereon, and an Si-containing resist 4 is applied on the resist 3 as the upper layer resist. Then, the upper layer resist 4 is exposed to light, a developing treatment is conducted, an aperture 5 is formed, and an O2-plasma etching treatment is conducted. To be more precise, the etchant of O2, plasma enters the aperture part 5 only, the lower layer resist 3 is etched, and when the etching makes progress as far as to the surface of the polysilicon film 2, an oxide layer 6 is formed. Then, the resists 3 and 4 are removed by the chemical solution such as a sulfated solution, and the unnecessary polysilicon layer 2 is removed by dry etching using the oxide layer 6 as a mask. Lastly, the oxide layer 6 is removed by conducting a selective dry etching using the gas such as fluorocarbon and the like, and a microscopic pattern such as a polysilicon gate or a wiring and the like is formed.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to the manufacture of semiconductor devices, in which a photosensitive Si-containing resist is used as the upper layer and a flattening resist is used as the lower layer in a method of direct writing with an electron beam. The present invention relates to a method for manufacturing with a two-layer resist.

(Conventional technology) FIG. 2 shows a conventional manufacturing method in cross section.

First, as shown in Figure (a), an oxide film 1 is formed on a semiconductor substrate, and a polysilicon film 2 is formed thereon. Then, as shown in FIG. 3B, a resist 3, which is the lower layer of the multilayer resist, is applied thereon.

And (C) As shown in the figure, there is a Si-containing resist 4 on top of it.
is applied to form a multilayer resist structure. Next, as shown in FIG. 3(d), the resist 4 is processed by photolithography to form openings 5. Thereafter, as shown in FIG. 3(e), etching is again performed using photolithography to form an opening up to the polysilicon film 2. 02 ion implantation (implantation) is performed into the opening 8 as shown in FIG. Thereafter, as shown in the figure (g), the resist 3.4 is removed by passing sulfuric acid.

Next, as shown in FIG. 3G, anisotropic dry etching is performed using a C1 gas using the oxide layer 6 as a mask, thereby forming a polycrystalline silicon pattern inverted with respect to the resist.

Then, as shown in the figure (h), the oxide layer 6 is removed by dry etching with a CF-based gas, thereby forming a polysilicon wiring pattern.

(Problem to be Solved by the Invention) However, at the stage shown in FIG. 3(e) in the manufacturing process described above, as shown in FIG. The shape becomes isotropic.

It is an object of the present invention to eliminate such drawbacks, make it easier to control the resist shape, and simplify the process.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention adopts a method in which the upper layer Si-containing resist pattern is used as a mask by 02 plasma in manufacturing using a multilayer resist, thereby patterning the lower layer resist. At the same time, the etching film in the opening was oxidized to form a pattern that was inverted with respect to the resist, and the etching film was etched using the oxide film as a mask.

(Function) Since the present invention uses the manufacturing method as described above, the resist shape can be easily controlled and the process can be simplified.

(Example) FIG. 1 shows a process sectional view of an example of the present invention, which will be described below.

First, as shown in FIG. 1(a), SiO2 is deposited on a semiconductor substrate.
□Film 1 is formed, and a polysilicon film is formed thereon.

The second film may be other film such as A1 instead of polysilicon. In short, it may be any material that ultimately satisfies the function of the gate wiring of the transistor. Then, as shown in (b),
A resist (a lower layer resist of a multilayer resist) 3 is applied thereon. Although the board appears flat in the diagram, it is actually an AI
Since there are steps due to other factors, a multilayer resist structure is used to control the resist shape.

Next, as shown in the figure (C), a Si-containing resist 4 is applied on the resist 3 as an upper layer resist.

Si-containing resists have good plasma resistance. After that (d)
As shown in the figure, the upper resist 4 is exposed to light and developed by direct writing with an electron beam to form openings 5.

The process up to this point is almost the same as the conventional method.

Here, in this embodiment, as shown in figure (e), 0
Etching with 2 plasma (conventionally ion implantation). The 02 plasma etchant enters only the opening 5 and etches the underlying resist 3, and when the etching progresses to the surface of the polysilicon film 2, an oxide layer 6 is formed. Since the upper resist 4 has good plasma resistance, etching progresses slowly and serves as a mask.

Next, as shown in FIG. 3(f), the resist 3.4 is removed with a chemical solution by passing sulfuric acid.

Next, as shown in (g), using the oxide layer 6 as a mask,
Dry etching is performed to remove unnecessary polysilicon layer 2. Dry etching is performed using a chlorine-based gas so that the polysilicon oxide layer 6 is selectively etched.

Finally, as shown in the figure (h), the acid underlayer 6 is removed by selective dry etching using a gas such as fluorocarbon. A fine pattern such as a polysilicon gate or wiring is formed using the manufacturing method described above.

If the film to be etched is AI, the following steps may be used.

In the step shown in FIG. 1(e), the portion 6 becomes an aluminum oxide (alumina) layer. If this alumina layer is etched under the conditions of a later process, the etching progresses ten times slower than aluminum, and therefore it can be used as an etching mask.

(f) In the process shown in the figure, the multilayer resist 3.4 is removed with concentrated nitric acid. (G) In the process shown in the figure, dry etching is performed using CCl4 and C12 gas using the alumina layer as a mask. That is, the aluminum is etched. When doing so, C
1. Increase the discharge frequency and pressure by increasing the flow rate (and CI"
(chlorine radicals) are the main etching species.

(h) When etching the alumina layer in the figure,
CCt, CCl by increasing the flow rate and lowering the frequency and pressure.
Remove by sputter etching with 5" ions as the main etching species.

(Effects of the Invention) As explained above, according to the manufacturing method of the present invention, the lower resist of the multilayer resist can be etched with 02 plasma (even if it is not 02), the etching film can be made into a layer with selectivity during etching, and the resist The oxide layer is removed by using a gas that can etch the resist (as shown in Fig. 3(b), b), and used as a mask to form an oxide layer on the etched film. Accurate control is possible, and process simplification can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the process of the present invention, FIG. 2 is a sectional view of the process of the conventional example, and FIG. 3 is a diagram illustrating problems. ■・・・・・・・・・S i O2 film, 2・・・・・・
...Polysilicon film, 3...Resist, 4...Si-containing resist, 5...
······Aperture. 6...... Oxidized layer. 1 to 0-m-sistor\゛su 1 1 attack 1 1 1
°−−−°Shun I ° Layer q Araz 7 Problem, q, L Orivision diagram Figure 3 Conventional IT 1st process 1st view Figure 2

Claims (1)

[Claims] When forming a pattern using a multilayer resist in the manufacture of semiconductor devices, after patterning the upper resist layer, when removing the lower resist layer based on the pattern, the lower resist layer is removed while being removed by O_2 plasma. A method of manufacturing a semiconductor device, characterized in that an oxide layer is formed that is selective to a portion that will not be etched in a later process, and is used as a mask during etching in a later process.