JPS616753A - Common memory device - Google Patents

Abstract

PURPOSE:To reduce the probability of competition with a common memory and to improve the efficiency of the whole system by forming a switching means for switching plural processors so as to access two or more common memory banks. CONSTITUTION:A common memory is divided into two or more common memory banks 31, 32, and when a processor accesses the common memory, a bank switching control circuit 35 selects which bank is accessed on the basis of address signals 121, 221 and sends selection signals 381, 382 to address selectors 331, 341 and data selectors 332, 342 to lead the address signals 121, 221 and data signals 122, 222 to common memory banks 31, 32. Simultaneously, bank selecting signals 361, 362 and read/write signal 371, 372 are outputted to the selected common memory banks 31, 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a common memory device I that is shared by a plurality of processors.

[Technical background of the invention and its problems]

In recent years, many multiprocessor systems have come into use, in which a single system includes a plurality of processors and performs arithmetic control in parallel.

These multiprocessor systems include those in which an arithmetic processor is tightly coupled to the main processor, those in which multiple processors are connected to a single bus, and those in which multiple processors are connected to multiple memories and ILOs in a matrix. be.

The most commonly adopted of these is the common memory method in which a single memory is shared by multiple processors. An example of this common memory type multiprocessor system is shown in FIG. 3 with two processors.

Each processor 10, 20 has a local bus 1
It has main memories 11 and 21 via processors 2 and 22, and programs and data executed by the respective processors 10 and 20 are stored in these main memories 11 and 21.

Furthermore, the local buses 12 and 22 are independent, and the respective processors 10 and 20 can perform operations independently and in parallel. The common memory 30 is used when data or programs need to be exchanged between these two processors 10 and 20.

In this example, the common memory 30 is accessed by two processors 10 and 20, so while it is being accessed by one processor, access by the other processor is delayed.

In this way, although the common memory method is most widely applied in multiprocessor systems, in the case of conventional methods, where access to the common memory is heavy, conflicting accesses always occur, and one side is forced to wait.
There is a problem in that the computational efficiency of the processor on the waiting side decreases, which in turn causes a decrease in the efficiency of the entire system.

[Purpose of the invention]

The present invention has been made in order to overcome the above-mentioned problems of the conventional common memory system, and it is an object of the present invention to provide a common memory device that reduces the probability of contention occurring even when access to the common memory is frequent. purpose.

[Summary of the Invention] In order to achieve the above object, the present invention provides a common memory device shared by a plurality of processors.
The common memory banks are divided into three or more common memory banks, and a switching means is provided for switching by the plurality of processors so that each common memory bank can be accessed independently, thereby reducing the probability of contention for the common memory and improving the efficiency of the entire system. This is a common memory device.

[Embodiments of the invention]

The main configuration of the present invention will be explained using the case where there are two processors as an example.
Shown in Figure 1.

In the example of FIG. 1, the common memory is divided into two or more banks 31.
, 32, and are provided with switching circuits O and 34 which are switched by commands from a processor (not shown) so that they can be accessed independently, thereby reducing access contention. That is, while one processor is accessing one bank of common memory,
The other processor can access the other bank of common memory. However, if two processors access the same bank of common memory at the same time,
Access contention occurs as before. Assuming that each processor's access to the common memory is randomly averaged over the entire common memory, if the common memory is divided into two, the contention rate will be reduced to %. The degree of reduction increases as the common memory is subdivided, but the control circuit becomes more complex. In the case of two processors, it is sufficient to divide the common memory into two and take into account how the common memory is accessed.

FIG. 2 shows an embodiment in which there are two processors and the common memory is divided into two banks.

The common memory according to the present invention has a bank switching control circuit 35
each common memory bank 31
, 32 and the bank selection signals 361, 362 and read/write signals 371, 37 for the respective common memory banks 31, 32.
Give 2.

The local bus leading from each processor 10, 20 to the common memory has an address signal 121122.
1, data signal 122, 222, memory read signal 1
23.223, memory write signals 124, 224, and response signals 125.225.

When access to the common memory occurs from either processor 10 or 20, the bank switching control circuit 3
5 selects which bank is to be accessed from the address signal 121, 221, and the respective address selectors 331, 341 and data selectors 332, 342
Selection signals 381 and 382 are sent to the memory banks 31 and 32, and address signals 121 and 221 and data signals 122 and 222 are guided to the common memory banks 31 and 32. At the same time, bank selection signals 361, 362 and read/write signals 37
1°372 selected common memory bank 31, 3
Output for 2. Then, after a predetermined access time/cycle time, output of bank selection signals 361, 362 and read/write signals 371, 372 is stopped, and response signals 125, 225 are output to processors 10, 20.

If there is an access from the other processor 10 or 20, the above processing is performed with priority given to the other processor 10.

After waiting until 20 accesses are completed, the above process is performed in the same way. However, you will only have to wait if the bank is the same.

By configuring and controlling the common memory as described above, while one processor is accessing one common memory bank, the other processor can simultaneously access the other common memory bank. Memory access contention can be reduced.

In this embodiment, the common memory is divided into two banks, but it can easily be divided into three or more banks, and the more finely divided the common memory is, the less likely there will be access conflicts. However, if they are divided too finely, the hardware of the address selector and data selector will increase, making it impossible to maintain a balance with respect to the memory elements, so the division should be decided in consideration of cost performance.

Further, in this embodiment, a case where one common memory is shared by two processors has been considered, but it can be easily extended to a case where there are three or more processors.

〔Effect of the invention〕

By using the common memory device according to the present invention, contention for accessing the common memory can be reduced, and the efficiency of the entire system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a main configuration diagram of the present invention, FIG. 2 is a detailed configuration diagram of an embodiment of the present invention, and FIG. 3 is a diagram illustrating a conventional common memory device. 10.20...Processor 11.21...Main memory 12.22...Local bus 30...Common memory 31.32...Common memory access 34...Switching circuit 35...Bank switching control Circuit 331.341...Address selector 332.342...Day/evening selector (7317) Representative patent attorney Kensuke Chika (and 1 other person) Fig. 1 Fig. 3

Claims (1)

[Claims] A common memory device shared by a plurality of processors, characterized by comprising switching means for dividing the common memory into two or more common memory banks and switching by the plurality of processors so that each common memory bank can be accessed independently. common memory device.