JPS6240565A - Memory control system - Google Patents

Abstract

PURPOSE:To improve the memory bus application ratio by receiving a memory access request as long as a memory bus is idle. CONSTITUTION:In the course of a read operation to a memory A, by utilizing a fact that an idle time is generated in a memory bus before the sending of a read data is started after an address is sent out, a write access request to a memory B is received, and an address and write data are sent out. That is to say, a memory request receiving control part 14 decides whether the requested memory is being operated or not, and whether the use time of a memory bus 20 overlaps or not, and when it is decided that the memory concerned is not being operated, and also the use time of the memory bus 20 does not overlap, an accepting signal is sent back to an access origin, a memory starting signal is sent to the control part of the memory concerned side, and a memory start instruction is executed. When the accepting signal is received, the memory access origin sends out an address to the memory bus 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory control method in a computer system in which a plurality of independently operable memories are connected to the same memory bus.

[Background of the invention]

In a computer system that uses a plurality of independently operable memories, one method of reducing memory access time is to provide the same number of memory buses as the number of memories. In this case, the number of memory buses increases as the memory increases, and the number of data lines between the memory and the memory access source increases.

When each memory control device or memory access source is composed of a large-scale integrated circuit, the input/output lines of each unit are limited, and it is desirable to reduce the number of data lines between units.A solution to this problem As a memory bus, multiple memories that can operate independently can be connected to each other through the same memory bus.
There is a way to connect to the access source.

Conventionally, when a plurality of memories are connected to the same memory bus, when one memory access operation is executed, the memory bus is occupied until the corresponding memory access operation is completed. As a result, when address information and data are transferred using the same memory bus in separate time blocks, the memory bus usage status during memory read operations is as shown in Figure 2, and the read data starts after the address is sent. There is idle time on the memory bus until the start of transmission. During this time, the memory in question is in operation, but other memories connected to the memory bus may be able to accept memory accesses. In the prior art, for example, Japanese Patent Application Laid-Open No. 1986-
As shown in Japanese Patent No. 963111, no consideration was given to the use of the memory bus during this free time.

[Purpose of the invention]

An object of the present invention is to improve the memory bus usage rate in a computer system equipped with multiple memories that can operate independently and multiple memory access sources, and to improve memory bus utilization without increasing the number of memory buses. The goal is to shorten memory access time.

[Summary of the Invention] In a computer system in which multiple memories, each of which can operate independently, are connected to the same memory bus, the present invention accepts memory access requests as long as the memory bus is free, and uses the memory bus to It should be used effectively. That is, as shown in FIG. 1, for example, during a read operation to memory A, a write access request to memory B is made by taking advantage of the free time that occurs on the memory bus between the sending of an address and the start of sending read data. reception, address,
It sends write data.

[Embodiments of the invention]

FIG. 3 is a system configuration diagram of an embodiment of the present invention, in which two memories 10° 11, each of which can operate independently, and three memory access source devices 15, 16° 17 are connected to the same memory.
An embodiment is shown connected via a bus 20. Memory access source 15 receives memory request from control unit 1
4, a memory access request is made using a memory request signal 21 and several auxiliary signals 22 indicating the type of memory request. When accepting a memory request, the control unit 14 determines whether the requested memory is not in operation and whether the usage times of the memory bus 20 do not overlap. If it is determined that they do not overlap, an accept signal 29 is sent back to the memory access source 15, and the corresponding memory, temporarily memory (A)
If it is 10.

The memory access source 15 sends a memory activation signal 27 to the memory A side control unit 12 to instruct the memory activation. When the memory access source 15 receives the accept signal 29, it sends an address to the memory bus 20. In the case of a write operation, write data is sent in the next cycle following the address, and the interface with the memory is completed. In the case of a read operation, after sending the address, the device waits for read data. Memory A side control section 12
Memory request reception operates based on a startup instruction from the control unit 14. In the case of a write operation, addresses and write data are sequentially fetched from the memory bus 20, and the memory (A
) Write data to the corresponding address of 10. In the case of a read operation, an address is fetched from the memory bus 20, the address is sent to the memory (A) 10, and the read data is sent to the memory bus 20 after a certain period of time. Memory access sources 16 and 17 and memory request reception are performed by the control unit 14
, and memory request reception are the same for the operations of the control unit 14 and the memory B side control unit 13.

Next, the operation of the control unit 14 for memory request reception will be explained. The relationship between the operating time of the memory-side control unit (MC) 12.13 and the usage time of the memory bus (MB) 20 is uniquely determined by the type of memory access operation. For example, it will look like Figure 4. FIG. 4 is an example when the memory bus width is n bytes. Therefore, the memory request reception is performed in the control unit 14 by providing a flag that is started corresponding to the memory and remembers the access operation, and a counter that indicates which stage the corresponding access operation is being executed. The operating time of the memory-side control unit 12, 13 can be found. As a result, memory access source 15,
It can be determined whether to accept a memory access request from 16.17.

In the system configuration example shown in Figure 3, the memory bus (MB
) 20 and the memory-side control unit (MC) 12-13 as shown in FIG. 4, and a memory access request occurs as shown in FIG. Furthermore, the reception of each memory access source 15°16.17 has priority order a.
> b > c.

The control unit 14 accepts the memory request at time t. At this point, an n-byte read request (nR request) 50 from the memory access source (a) 15 to the memory (A) 10 is accepted, and the memory A side control unit 12 is activated. As a result, the memory A side control section 1
2 is busy (MCA busy), and 10-1.
During the period, the memory access source (a) 15 accesses the memory (A
) 10 (aA address) is connected to the memory bus (
MB) 20, 1. -18 period of memory (A
) 10 to memory access source (a) 15.
Data (aA read data) is sent to memory bus 20.

At time t2, a 2n byte write request (2nW request) 51 is sent from the memory access source (b) 16 to the memory (B) 11, and a request is made from the memory access source (c) 17 to the memory (
B) An n-byte write request (nW request) 52 to 11 is issued. At this time, when we examine the usage time of the memory bus 20, we see from FIG. 4 that the 2n byte write operation is 14-1.
Since the period 5 overlaps with the n-byte read operation of the memory access source (a) 15, the control unit 14 does not accept the 2nW request 51 from the memory access source (b) 16. Memory access source (c) 17 is the memory access source (c) 17.
It has a lower priority than access source (b) 16, but the memory
Since it does not overlap with the n-byte read operation of the access source (a) 1.5, the control unit 14 accepts the nW request 52 from the access source (c) 17 to the memory (B) 11, and the memory B side The control unit 13 is activated. This results in
The memory B side control unit 13 becomes busy (MCBbusy
), jz-t3p tz t, the address (cB address) and write data (cB write data) from the memory access source (c) 17 to the memory (B) 11 are transferred to the memory bus (MB) 20. will be sent to.

FIG. 6 is a detailed diagram of the control unit 14 for accepting memory requests.

Memory request reception is performed by a memory side control unit (M
C) There is an MCA control unit 60 and an MCB control unit 61 for 12.13. For example, the memory request signal 21 and memory request auxiliary signal 22 from the memory access source (a) 15 are sent to the request type determination unit 62 in the MCA control unit 60.
sent to. The request type determination unit 62 determines the type of requested memory access, refers to the busy signal 67 of the corresponding access operation, and sends the memory access request determined not to be busy via the type-specific request line 69. , is sent to the priority determination section 63. The priority determination unit 63 performs priority determination between memory access sources and sends an accept signal to the accepted memory access source. For example, when memory access source (a) 15 is accepted, signal IPI 70 is ORed by OR circuit 71,
Becomes an accept signal 29 and memory access source (a)
Sent to 15. At the same time as returning the accept signal, the priority determination section 63 issues a startup instruction to the memory A side control section 12, and starts the stage counter 64.

The MCA busy flag 65 is set, and the request type display flag 73 is set for reception. The stage counter 64 counts different values depending on the type of access operation. The stage counter 64 and the reception are processed by the bus/busy generation unit 7 according to the value of the request type display flag 73.
4 informs the MCB control section 61 of the memory bus use time of the memory (A) 10 through a signal line 72. The busy signal 67 is a signal indicating that the corresponding memory is available and that memory bus usage does not overlap.

It is created by ORing the MCA busy flag 65 and the signal line 68 from the MCB control unit 61 to inform the memory bus usage time of the memory (B) 11 using the OR gate 66. M
CA busy flag 65 is reset by the value of stage counter 64.

The MCB control section 61 performs the same processing as the MCA control section regarding the memory (B) 11.

〔Effect of the invention〕

As described above, according to the present invention, in a system having multiple memories that can operate independently and multiple memory access sources, the memory bus usage rate can be improved and each memory can be accessed without increasing the number of memory buses.・The memory access time from the access source can be shortened. For example,
In the system shown in Figure 3, if the same number of read access requests and write access requests occur to two different memories, all write access operations are performed while the read access is being executed, and the memory bus is connected to the memory. to 2
Memory access can be performed in the same memory access time as when this arrangement is provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the basic concept according to the present invention, FIG. 2 is a diagram explaining the conventional method, FIG. 3 is a system configuration diagram of an embodiment of the present invention, and FIG. 4 is an access operation and memory bus diagram. A timing diagram showing the relationship between the usage time and the busy state of the memory-side control unit. Figure 5 is a timing diagram showing an example of memory requests and memory bus usage. Figure 6 shows details of the memory request reception in Figure 3 and the control unit. It is a diagram. 10.11...Memory, 12.13...Memory side control unit, 14...Control unit accepts memory request,
15.16.17...Memory access source device, 20
...Memory bus, 21,23.25...Memory request signal, 22,24,26...Memory request auxiliary signal, 27.28...Memory activation signal. 29.30,31...Accept signal. 62...Request type determination unit, 63...Priority determination unit, 64...Stage callan, ri, 65...
- Busy flag, 73... Request type display flag for reception, 74... Bus busy creation section. Access 1ui Ashi

Claims (1)

[Claims] (1) A system in which a plurality of memories, each capable of operating independently, are connected to the same memory bus, and a memory access acceptance control unit accepts a memory access request from a memory access source and controls the use of the memory bus. In this case, the memory access acceptance control unit is provided with means for predicting the time that the memory bus will be used in the accepted memory access operation, and when the memory access source makes a memory access request, the corresponding memory is in operation. and if the memory bus usage time does not overlap between the already accepted memory access operation and the memory access operation due to the corresponding memory access request, the corresponding memory access request is accepted. .