JPH0350301B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control method for a vector processor, and is intended to achieve memory access without bus contention.

[Prior Art] In recent years, demands on vector processors have been increasing. This is due to the need for large-scale calculations that cannot be processed by general-purpose ultra-large computers in the fields of science and technology. A vector processor processes a large amount of vector data at high speed, and its memory access function is required to have a high-speed arithmetic unit and a high throughput for supplying a large amount of data to the arithmetic unit.

Vector data is a collection of data, and each vector data consists of data called multiple elements. In a normal vector processor, one vector data consists of element numbers 0 to
It consists of N-1 elements, and all of these N elements are subjected to the same processing by one vector instruction, thereby speeding up the processing. Each element is typically a piece of floating point, fixed point, or logical data.

A vector processor's memory access requires a throughput that cannot be compared to that of a normal general-purpose computer, but to achieve this, the vector processor's memory control unit (MCU, which controls memory access priority) requires special control. It is common practice. For example, in a normal general-purpose computer, even if it is a very large computer, the MCU can only access one request (REQ) in one cycle, but a vector processor allows multiple requests to be accessed in one cycle. is normal.

In order to allow access by multiple requests in one cycle, it is necessary to have multiple ports in the MCU,
It is necessary to connect multiple address buses and data buses from the MCU to the memory (MSU, main storage unit). An example is shown in FIG. Second
In the figure, eight buses are connected between the MCU and MSU. These are address buses, but the data buses are also not shown, but each MSU block MSU ₀ ~
Attached to MSU ₇ . This memory MSU is divided into banks, m of which constitute one block.
There are 8 blocks. Each bank is interleaved, and banks 0, 1, 2,...7 are interleaved with blocks 0, 1, 2,...7 (MSU ₀ , MSU ₁ , MSU ₂ ,
. . MSU ₇ ), banks 8, 9, 10, . . . 15 are placed in blocks 0, 1, 2, . . . 7, and so on.

Vector processor memory access requests are
It is set in a memory access request register called a port, and priority control is performed as to whether or not memory access is possible. Ports are 101-104
There are four (these are referred to as A to D systems), and each memory access request (REQA to D, which includes an address) is sequentially fetched by creating a queue (REQ queue A to D). The access request REQ that has been decided to be adopted as a result of priority control is set in a register MSAR (main storage address register) connected to the corresponding MUS block according to the address to be accessed, and a memory access request is transmitted. For example, if the address at 101 of port A accesses bank 0 of MSU ₀ , the address of that port will be assigned to multiplexer 1.
MSAR is set to 106 by 05,
Sent to MSU ₀ . A portion of the address sent to memory block MSU ₀ is branched by power gate 116 and becomes an address for accessing each bank. The remainder of the address becomes a signal (valid signal) for selecting one of the banks 0 to 8m of the block. Although not shown, store data is also selected corresponding to each MSU block in the same way as addresses.
Sent to the relevant MSU block. Data read by MSU access is sent from the selected bank within the MSU to the MSU.

[Problem that the invention seeks to solve]

In this memory access method, the address register
There are problems in that contention tends to occur in the MSAR (or bus), access is delayed, and the amount of access processing cannot be increased significantly. For example, if the address of a memory access request from port A is for accessing bank 0 of MSU ₀ , and the address of a memory access request for port B is for accessing bank 8 of MSU ₀ , the MSAR 106 identifies port A and Port B contention occurs. Therefore, a memory access request for either port A or port B is delayed by one cycle due to priority processing at multiplexer 105. In this way, although the system is configured to be able to execute a plurality of memory accesses at the same time, and even though the access target (bank) is not busy, the system is delayed by one cycle, resulting in degraded system performance.

Vector processor memory access is continuous access: data stored in consecutive addresses in memory is accessed one after another.Equidistant access: data stored in discrete addresses spaced apart at equal intervals in memory is accessed one after another. There are three types: interval specified access, which accesses by an indirectly specified address, and the address is random and has no regularity. In matrix calculations (vector calculations), each element in a row is multiplied by each element in a column, but if data is stored in memory in the row direction (raster scan direction), each row direction The access to retrieve an element is as described above, and the access to retrieve each element in the column direction is as described above.

When there is a sufficient distance between equally spaced accesses and when accesses are made using indirect address addresses, it is necessary to guarantee the order of stores in a series of store operations. This is to avoid the problem that when the address of the lower element number and the address of the higher element number are equal and the store order is different, the result of the program will be different. You can avoid this by accessing them in numerical order.
That is, the access whose store order is number K must be activated before the access whose store order is number K+1.

Memory access requests in the access order 0, 1, 2, ... are sent to queues 140 to 14 as shown in FIG.
3 and ports 101-104. In this figure, E0, E1, E2, . . . indicate the memory access requests (E indicates the element). If E0 and E1 both access MSU ₀ , E1 will not be activated and E2 will also access E1.
is delayed because it does not start. Even if E2 accesses a different MSU block than E1. Thus, the address register
When contention occurs in MSAR, accesses are delayed and
If ordering is guaranteed, non-conflicting accesses will be delayed, resulting in a significant drop in performance. For example, indirect specified access, 4 MSU blocks, 4 ports
Assuming that there is no order guarantee (there is no mutual interference between accesses between ports), the expected value P at which accesses of four ports can be activated is P = 1 + 3/4 + 2/4 + 1/4 = 2.5, and the order is guaranteed. If there is, P=1+3/4+3/4×2/4+3/4×2/4×1/4=2.21. Since the maximum expected value is 4, the performance drop due to bus contention is significant, and if the order is guaranteed, the performance will drop even further. Guaranteed access order is logically necessary as long as multiple ports are used to perform multiple data load/store accesses by one memory access command, and cannot be avoided.

In order to avoid such performance degradation, the present invention aims to provide a memory access method that does not cause bus contention.

[Means for solving problems]

The present invention is a memory access control method for a vector processor that processes large amounts of data at high speed. A multiplexer that supplies addresses to banks and valid signals for banks and blocks, and a multiplexer that supplies addresses to banks and valid signals for banks and blocks, and multiple memory access request addresses inputted from multiple ports of the memory control device that have orderly access to the same block and the same bank. a priority circuit that simultaneously outputs to each of the multiplexers except those accessing the multiplexer; the priority circuit inputs one or more input addresses to the multiplexer; According to an input address, an address is supplied to a bank corresponding to the address and a valid signal for the bank and block is output.

[Effect]

By bringing all the memory access request addresses of each port to the memory block and making it possible to individually set any of the request addresses for all banks using a multiplexer, access conflicts can be avoided unless the same block or bank is being accessed. The throughput of the memory access control system can be greatly improved.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and parts similar to those in FIG. 2 are given the same reference numerals. The memory MSU also has a bank and block configuration, and the number of blocks is 4, banks 0, 1, 2, etc. are block 0 (MSU ₀ , 218), block 1 (MSU ₁ ,
219), block 2 (MSU ₂ , 220), and so on. Each block consists of one or several memory cards. Memory MSU, memory control unit
The number of buses between MCUs is the same as the number of ports, and a multiplexer MPX is placed in each block of the MSU.
The priority control circuit 205 simply checks whether each memory access request of each port can be activated, and if it is an activation function, it registers the request.
MSAR and sends a memory access request to the MSU. Memory address register (MSAR)
206-209 are those in Figure 2 MSAR106-
113, in FIG. 2 it is for each MSU block, whereas in FIG. 1 it is common to all MSU blocks and corresponds to each port. Note that FIG. 1 also shows only the address system and does not show the data system.

The memory access request and its address set in the memory address register MSAR are sent to the MSU, branched by power gates 210-213, and sent to memory blocks 218-221. Some of the addresses sent to each memory block 218-221 are sent to multiplexers 214-217.
The rest of the address is sent to the corresponding bank by block selection (block valid). The above address to access each bank,
A register is provided to hold store data and the like for the cycle time in one-to-one correspondence with each bank, but this is not shown.

As can be seen from FIG. 1, memory access requests from each port do not interfere with each other unless they access the same bank. For example, if each memory access request of port A and port B accesses bank 0 and bank 4 of memory block 218, both requests can access the memory together without causing any conflict. Memory access requests entering different ports that access the same bank of the same memory block cause these conflicts and
MPX may cause confusion by transmitting addresses from each port to the same bank. This point is checked by the priority control circuit 205 of the MCU, and access requests for the same block and the same bank from different ports are processed with priority and one is delayed.
If the access order is guaranteed, other accesses will also be delayed at the same time.

The address for accessing the memory consists of an intra-bank address, a bank address (bank number), a block address (block number), etc. The intra-bank address is input to each bank simultaneously through the multiplexer MPX to select memory cells within the bank. The bank address and block address are decoded in a multiplexer, and the decoded output is supplied to each block and each bank to make the corresponding block and bank valid and the others invalid.

〔Effect of the invention〕

According to this access control method, all memory access request addresses of each port are brought to each memory block, and the address of any port can be individually set for all banks using a multiplexer. There is no competition except for accesses to the same bank, and access processing performance can be improved. In the conventional method, contention occurs if the blocks to be accessed are the same, so contention occurs frequently when the memory capacity of the block is large (large number of banks), but with the method of the present invention, this does not occur and it is possible to use large blocks. I can do it. Also, from the memory controller MCU to the memory MSU
In the conventional method, the number of buses connected to the bus is equal to the number of blocks, but in the method of the present invention, it is equal to the number of ports.
This part can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is an operation explanatory diagram. In the drawing, MSU is a memory, MCU is a memory control unit, 218 to 221 are banks, MPX is a multiplexer, and 101 to 104 are ports.

Claims (1)

[Claims] 1. In a memory access control system for a vector processor that processes large amounts of data at high speed, each block of memory is divided into many banks and interleaved to form a plurality of blocks.
providing an address to each bank within the block;
In addition, a multiplexer that supplies bank and block valid signals and multiple memory access request addresses inputted from multiple ports of the memory control device that are accessed in an orderly manner are simultaneously processed, except for those that access the same block or the same bank. It has a priority circuit that outputs to each of the multiplexers, the priority circuit inputs one or more input addresses to the multiplexer, and the multiplexer outputs the address according to the one or more input addresses given. A memory access control method characterized by supplying an address to a bank corresponding to the address and outputting a valid signal for the bank and block.