JPS6164744U - - Google Patents
Info
- Publication number
- JPS6164744U JPS6164744U JP14991184U JP14991184U JPS6164744U JP S6164744 U JPS6164744 U JP S6164744U JP 14991184 U JP14991184 U JP 14991184U JP 14991184 U JP14991184 U JP 14991184U JP S6164744 U JPS6164744 U JP S6164744U
- Authority
- JP
- Japan
- Prior art keywords
- source
- transistor
- output
- load
- drive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の高電圧出力駆動回路、第２図
は従来の同回路、第３図は本考案の同回路の他の
実施例を示す。
主な図番の説明、８…入力端子、９，１０…ス
イツチングトランジスタ、１１…駆動トランジス
タ、１２…負荷トランジスタ、１３…出力トラン
ジスタ、１４…負荷、１５…低電圧端子、１６…
高電圧端子。
FIG. 1 shows a high voltage output drive circuit according to the present invention, FIG. 2 shows a conventional circuit, and FIG. 3 shows another embodiment of the same circuit according to the present invention. Explanation of main figure numbers, 8...Input terminal, 9, 10...Switching transistor, 11...Drive transistor, 12...Load transistor, 13...Output transistor, 14...Load, 15...Low voltage terminal, 16...
High voltage terminal.
Claims (1)
スイツチングトランジスタと、該スイツチングト
ランジスタの出力端に接続されると共に前記第１
の直流源より高い電圧を有する第２の直流源に接
続され、負荷インピーダンスを有する駆動トラン
ジスタと、該駆動トランジスタの出力端に接続さ
れると共に前記第２の直流源に負荷を介して接続
された出力トランジスタとより成り、前記スイツ
チングトランジスタの入力端に入力信号を印加し
、前記出力トランジスタのオン時前記負荷を前記
第２の直流源により駆動することを特徴とした高
電圧出力駆動回路。 a switching transistor connected to a first direct current source having a predetermined voltage;
a drive transistor connected to a second DC source having a higher voltage than the DC source and having a load impedance; and a drive transistor connected to the output terminal of the drive transistor and connected to the second DC source via a load. A high voltage output drive circuit comprising an output transistor, wherein an input signal is applied to an input terminal of the switching transistor, and when the output transistor is on, the load is driven by the second DC source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14991184U JPS6164744U (en) | 1984-10-03 | 1984-10-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14991184U JPS6164744U (en) | 1984-10-03 | 1984-10-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6164744U true JPS6164744U (en) | 1986-05-02 |
Family
ID=30708077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14991184U Pending JPS6164744U (en) | 1984-10-03 | 1984-10-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6164744U (en) |
-
1984
- 1984-10-03 JP JP14991184U patent/JPS6164744U/ja active Pending
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