JPS61174213U - - Google Patents
Info
- Publication number
- JPS61174213U JPS61174213U JP5842485U JP5842485U JPS61174213U JP S61174213 U JPS61174213 U JP S61174213U JP 5842485 U JP5842485 U JP 5842485U JP 5842485 U JP5842485 U JP 5842485U JP S61174213 U JPS61174213 U JP S61174213U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- voltage power
- power supply
- switch means
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案実施例の増幅回路の回路図、
第２図は従来の増幅回路の回路図である。
１ａは第１トランジスタ、４は入力端、Ｖｂは
定電圧源、２ａは低電圧電源、１ｂは第２トラン
ジスタ、２ｂは高電圧電源、３ａ，３ｂ，３ｃは
それぞれスイツチ手段である。
Figure 1 is a circuit diagram of an amplifier circuit according to an embodiment of this invention.
FIG. 2 is a circuit diagram of a conventional amplifier circuit. 1a is a first transistor, 4 is an input terminal, Vb is a constant voltage source, 2a is a low voltage power source, 1b is a second transistor, 2b is a high voltage power source, and 3a, 3b, and 3c are switch means, respectively.
Claims (1)
タ１ａに接続された入力端４と、当該入力端４に
接続された定電圧源Ｖｂと、前記第１トランジス
タ１ａに接続された低電圧電源２ａと、第２トラ
ンジスタ１ｂと、高電圧電源２ｂと、前記低電圧
電源２ａ又は前記高電圧電源２ｂのいずれか一方
を選択的に前記第２トランジスタ１ｂに接続する
スイツチ手段３ａと、前記第２トランジスタ１ａ
を負荷５又は前記第１トランジスタのいずれか一
方に選択的に接続するスイツチ手段３ｂと、前記
第１トランジスタを入力端又は定電圧源のいずれ
か一方を選択的に接続するスイツチ手段３ｃを具
備し、前記負荷５のインピーダンスが設定値より
小さい場合前記スイツチ手段３ａ，３ｂ，３ｃが
それぞれ低電圧電源２ａ、負荷５、入力端４に接
続されるようにしたことを特徴とする増幅回路。 A first transistor 1a, an input terminal 4 connected to the first transistor 1a, a constant voltage source Vb connected to the input terminal 4, a low voltage power source 2a connected to the first transistor 1a, and a first transistor 1a. 2 transistor 1b, a high voltage power supply 2b, a switch means 3a for selectively connecting either the low voltage power supply 2a or the high voltage power supply 2b to the second transistor 1b, and the second transistor 1a.
switch means 3b for selectively connecting the first transistor to either the load 5 or the first transistor; and a switch means 3c for selectively connecting the first transistor to either the input end or the constant voltage source. . An amplifier circuit characterized in that when the impedance of the load 5 is smaller than a set value, the switch means 3a, 3b, 3c are connected to the low voltage power supply 2a, the load 5, and the input terminal 4, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5842485U JPS61174213U (en) | 1985-04-18 | 1985-04-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5842485U JPS61174213U (en) | 1985-04-18 | 1985-04-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174213U true JPS61174213U (en) | 1986-10-30 |
Family
ID=30583908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5842485U Pending JPS61174213U (en) | 1985-04-18 | 1985-04-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174213U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58111507A (en) * | 1981-12-25 | 1983-07-02 | Nippon Gakki Seizo Kk | Power amplifier |
-
1985
- 1985-04-18 JP JP5842485U patent/JPS61174213U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58111507A (en) * | 1981-12-25 | 1983-07-02 | Nippon Gakki Seizo Kk | Power amplifier |
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