JPH02137131U - - Google Patents
Info
- Publication number
- JPH02137131U JPH02137131U JP4651289U JP4651289U JPH02137131U JP H02137131 U JPH02137131 U JP H02137131U JP 4651289 U JP4651289 U JP 4651289U JP 4651289 U JP4651289 U JP 4651289U JP H02137131 U JPH02137131 U JP H02137131U
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- potential
- connection point
- bias voltage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
及び第３図は従来例を示す回路図である。
６……電流出力端子、７……第１のＭＯＳトラ
ンジスタ、８……第２のＭＯＳトランジスタ、９
……第３のＭＯＳトランジスタ、１０……第４の
ＭＯＳトランジスタ、１１……インバータ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing a conventional example. 6... Current output terminal, 7... First MOS transistor, 8... Second MOS transistor, 9
...Third MOS transistor, 10... Fourth MOS transistor, 11... Inverter.
Claims (1)
のバイアス電圧が印加された第１のＭＯＳトラン
ジスタ、及び、第２のバイアス電圧が印加された
第２のＭＯＳトランジスタと、 前記第１のＭＯＳトランジスタと第２のＭＯＳ
トランジスタの接続点と第２の電位の間に設けら
れた第３のＭＯＳトランジスタと、 前記第１の電位と前記接続点の間に接続された
第４のＭＯＳトランジスタと、 入力が前記接続点に接続され、出力が前記第４
のＭＯＳトランジスタのゲートに接続されたイン
バータと、 を備えてなる定電流セル回路。[Claims for utility model registration] The first electric potential is connected in series between the first potential and the output terminal, and the first
a first MOS transistor to which a bias voltage of is applied; a second MOS transistor to which a second bias voltage is applied; the first MOS transistor and the second MOS transistor;
a third MOS transistor provided between a connection point of the transistor and a second potential; a fourth MOS transistor connected between the first potential and the connection point; and an input connected to the connection point. connected and the output is the fourth
A constant current cell circuit comprising: an inverter connected to the gate of a MOS transistor;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4651289U JPH02137131U (en) | 1989-04-20 | 1989-04-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4651289U JPH02137131U (en) | 1989-04-20 | 1989-04-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02137131U true JPH02137131U (en) | 1990-11-15 |
Family
ID=31561656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4651289U Pending JPH02137131U (en) | 1989-04-20 | 1989-04-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02137131U (en) |
-
1989
- 1989-04-20 JP JP4651289U patent/JPH02137131U/ja active Pending
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