JPS615491A - Read out adjusting circuit - Google Patents

Abstract

PURPOSE:To read out securely data from an integrated circuit long in access time by providing a latch circuit for outputting continuously data for the time longer than the access time of the integrated circuit and a latch circuit keeping the data when the data of the integrated circuit is established. CONSTITUTION:A read signal R is continuously latched for the time longer than the access time of an integrated circuit 13 such as an arithmetic circuit in a latch circuit 12 where an enable signal at a high level from a monostable multivibrator 11 turns out to be a latch command. On the other hand, a latch circuit 15 is controlled by the circuit 13. After data of the circuit 13 is established, output data of the circuit 13 is latched and outputted. Thus data can be securely read out from the integrated circuit with a long access time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a read adjustment circuit used for an integrated circuit having a long read access time, such as an integrated circuit for arithmetic operations.

(Background of the Invention) The basic hardware configuration of a microcomputer device, as shown in FIG. 4, includes an arithmetic processing unit 1, a decoder circuit 2. Integrated circuits 3a, 3b such as ROM and RAM,
3c is connected by an address line 4, a cheater line 5% control line 6, and a chip select line 7. Arithmetic processing unit 1 and integrated circuits 3a to 3C
The timing of signal exchange between the two is set so as to satisfy the respective required time characteristics. FIG. 5 is a time chart of the read operation.

Read and write operations of the arithmetic processing device 1 are performed using the basic clock signal E as a reference. After a time t1 from the fall of the basic clock signal E, the decoder circuit 2 outputs a chip select signal v100 and selects a predetermined integrated circuit 3a, 3b or 3C.
is selected. Simultaneous K.

The arithmetic processing device 1 inverts the control signal R/W to 71 levels and instructs reading. integrated circuit 3a,
3b or 3C sends a data signal to the arithmetic processing unit 1 via the data line 6 after the read access time t has elapsed. The arithmetic processing unit 1 reads the data signal, but for this purpose it must wait a time t with respect to the fall of the basic clock signal E.
It is necessary that the data signal be established before 3, and that the data signal be established during time t4 after the fall. In FIG. 5, there is a margin time t between the read access time t and the time t, l, and the read operation can be completed within a read cycle corresponding to one cycle of the basic clock signal E.

However, some high-performance integrated circuits and special integrated circuits, such as integrated circuits for calculations, have read access times t,
may not fit within one cycle of the basic clock signal E. In this case, the frequency of the basic clock signal E can be delayed to match the integrated circuit with the longest read access time t, but this will slow down the overall operation.

In order to eliminate this drawback, some arithmetic processing units are equipped with a memory ready signal input terminal for extending the basic clock signal E. If this is shown in FIG. 6, the integrated circuit 3d commands readout,
When a read operation is started by /W, a busy signal MO is output, which is sent to the processing unit 1 as a memory ready signal M.
Send as Tt. Thereby, the arithmetic processing device 1 extends the period of the basic clock signal E. When the integrated circuit 3d determines the data signal, it stops outputting the busy signal MO, and
Therefore, the arithmetic processing device 1 cancels the extension of the basic clock signal E, returns to normal read operation, and reads the data signal. In many cases, the number of cycles is limited due to data guarantee, etc. Therefore, the read access time is 1. cannot be used for very long integrated circuits. Furthermore, some arithmetic processing units 1 do not have a memory ready signal input terminal, and therefore such units cannot operate integrated circuits that require a long read access time.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a read conditioning circuit that is capable of reading data signals from integrated circuits with a considerably long read access time.

(Features of the Invention) In order to achieve the above object, the present invention holds a read signal by a latch command signal and continues the read signal for a period longer than the read access time for an integrated circuit having a long read tick access time. a first latch circuit that outputs the data signal from the integrated circuit; and a second latch circuit that holds the data signal when the data signal of the integrated circuit is determined; It is characterized by being able to read data signals.

(Embodiments of the Invention) FIG. 1 shows two embodiments of the invention which are read-only.
The figure shows the time chart.

When the -th chip select signal C81 is input to the monostable multivibrator IIBC, the monostable multivibrator 11 applies a no-y level signal MM to the enable terminal ENAk of the latch circuit 12, thereby putting the latch circuit 12 into a latchable state. The time tll of the signal MM is determined to be a time that can sufficiently read the data signal from the integrated circuit 13 which has a long read access time. When both the chip select signal C8 and the basic clock signal E become high level, the AND gate 14 inputs a high level signal to the clock terminal CLK of the latch circuit 12, and the latch circuit 1
2 latches the read signal R that has been input from the arithmetic processing unit from time 111 before latching, and then from time t's
During this period, the read signal W is continuously outputted to the integrated circuit 13.

The integrated circuit 13 starts a read operation, and when the data signal is aligned with the data line, it inputs a pause signal P to the clock terminal CLK of the latch circuit 15, which proves that the data signal is fixed. As a result, latch circuit 1
5 latches the data signal and continuously outputs it as a data signal. The read access time t14 is from when the read signal R' is input to the integrated circuit 13 until when the pause signal P is output. The latch circuit 15 latches the signal as described above.

The data signal σ is input to the receiver circuit 16. The receiver circuit 16 is of three states, and when the second chip select signal C8 is input, it outputs the data signal U to the arithmetic processing unit.

After the arithmetic processing unit outputs the read signal R, until the integrated circuit 13 determines the data signal.

I can do other jobs.

High level (i) from monostable multivibrator 11
When the signal M is inverted to low level, the latch circuit 12
Since the latch state is released and the output of the read signal D' is stopped, the integrated circuit 13 will not read out the data signal again by mistake.

The receiver circuit 16 is in a high impedance state when there is no control input, but the second chip select signal CS
, is input as a control input, the data signal υ output from the latch circuit 15 is sent as is to the arithmetic processing device, so that the arithmetic processing device can sufficiently read the data signal D'.

FIG. 3 shows another embodiment of the invention that is capable of both reading and writing. The readout operation is almost the same as the embodiment shown in FIG. The difference is that 17 high level outputs are used.

During the write operation, the chip select signal C81 and the write signal W are input to the AND gate 18, so that
The AND gate 18 inputs the high level write signal W' to the integrated circuit 13VC and drives the driver circuit 19. As a result, the driver circuit 19 transfers the data signal "Dw" sent from the arithmetic processing device to the integrated circuit 13.
have it written in. The timing of the write operation is well within one cycle of the basic clock signal E.

During the write operation, the latch circuit 12 is in a high impedance state because the high-level signal MM from the monostable multivibrator 11 is not input, so that the write signal W is sufficiently applied to the integrated circuit 13.

Note that the driver circuit 19 is also of three states, and is in a high impedance state during a read operation because no write signal W is input. Therefore, the data signal output from the convex integrated circuit 13 is output from the latch circuit.
.

15 is given enough.

(Effects of the Invention) As explained above, according to the present invention, a read signal is held by a latch command signal, and the read signal is continued for a longer period than the read access time to an integrated circuit having a long read access time. a first latch circuit that outputs the data signal from the integrated circuit; and a second latch circuit that holds the data signal when the data signal of the integrated circuit is determined; Because the data signal is read, it is possible to read the data signal from an integrated circuit having a relatively long read access time. Further, even when using an arithmetic processing device without a memory ready signal input terminal, data signals can be read from an integrated circuit that requires a long read access time.

Furthermore, data signals can also be read out from integrated circuits that operate with another clock signal that is unrelated to the basic clock signal of the processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart showing its operation, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram showing the basic configuration of a conventional microcomputer device.
FIG. 5 is a time chart showing its operation, and FIG. 6 is a block diagram showing a conventional arithmetic processing device equipped with a memory ready signal input terminal. 11... Monostable multivibrator, 12.
・°...Latch circuit, 13...Integrated circuit, 1
4...AND gate, 15...Latch circuit, 16...Receiver circuit, E...
Basic clock signal, cs, cs,...Chip select signal, R, R'...Read signal, D,
D'...Data signal, P...Pause signal. Figure 1, figure 2, figure 4, figure 5, figure 6, figure 6.

Claims (1)

[Claims] 1. A first latch circuit that holds a read signal according to a latch command signal and continuously outputs the read signal to an integrated circuit having a long read access time for a period longer than the read access time; and the data of the integrated circuit. and a second latch circuit that holds the data signal once the signal is determined.