JPH0635845A - Access control circuit device - Google Patents

Abstract

PURPOSE:To provide an access control circuit device which can work at a high speed even in the access to an external circuit. CONSTITUTION:A semiconductor integrated circuit device contains a CPU 1 and the peripheral circuits 3a and 3b and performs a DMA operation between both circuits 3a and 3b when the CPU 1 is kept waiting. Meanwhile, an access control circuit device controls the access action carried out to another semiconductor integrated circuit device. In such a constitution, the information transmission control means 4 are added to control the transmission of addresses and data, respectively, between the CPU 1 and another semiconductor integrated circuit device. Furthermore, a control means 6 sends a CPU control signal to the CPU 1 and also sends the transmission control signals to both means 4 and 5 when the CPU 1 has an access to another semiconductor circuit device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access control circuit device which can operate at high speed when a semiconductor integrated circuit composed of, for example, one chip accesses an external peripheral circuit.

[0002]

2. Description of the Related Art A central processing unit (hereinafter referred to as C
A semiconductor integrated circuit including a PU) and an external circuit that operates at a speed slower than that of the CPU and is provided separately from the semiconductor integrated circuit, and the CPU accesses the external circuit. In this case, the operation speed of the external circuit is slow, so as shown in (c) of FIG.
It is necessary to supply the IT signal and extend the arithmetic processing cycle of the CPU to multiple times for access.

Thus, conventionally, the operation of the CPU is in a stopped state while the arithmetic processing cycle of the CPU is extended. Therefore, particularly in a CPU that operates at high speed, and when the number of accesses to an external circuit whose operation speed is slow is high, the operation of the CPU becomes very inefficient and the operation speed of the entire system becomes slow. There is a point.
The present invention has been made to solve such a problem, and an object thereof is to provide an access control circuit device capable of operating at high speed even when a CPU accesses an external circuit.

[0004]

SUMMARY OF THE INVENTION The present invention has a CPU connected to an address bus and a data bus and a peripheral circuit of the CPU, and direct memory access between the peripheral circuits when the CPU is in a wait state. In an access control circuit device for controlling an access operation between a semiconductor integrated circuit device that performs an operation and another semiconductor integrated circuit device different from the semiconductor integrated circuit device, the address bus and the data bus and the other Information transmission control means connected between the semiconductor integrated circuit device and the CPU for controlling address and data transmission between the CPU and the other semiconductor integrated circuit device, and the CPU to the other semiconductor integrated circuit device. When access is made, a CPU control signal is sent to the CPU, and the information transmission control means is provided for controlling the transmission. And a control means for sending a control signal, characterized by comprising a.

[0005]

With this configuration, the control means can control the CP
The U control signal controls the CPU operation, and the information transmission control means controls the timing of information transmission between the CPU and another semiconductor integrated circuit device by the control signal supplied from the control means. The information transmission control means stops the data transmission from the other semiconductor integrated circuit device to the CPU when the CPU is in the wait state by the CPU control signal, for example.
It acts to safely perform the DMA operation between the peripheral circuits, and to provide an access control circuit device that can operate at high speed even when the CPU accesses the other semiconductor integrated circuit device.

[0006]

【Example】

First Embodiment: An embodiment of the access control circuit device of the present invention will be described below with reference to FIG. The access control circuit device in this embodiment includes a CPU 1, an address latch circuit 4 for latching an address sent by the CPU 1 to the external circuit 9, and a data latch circuit 5 for latching data transmitted between the CPU 1 and the external circuit 9. , A control circuit 6 for supplying a control signal such as a WAIT signal which is a CPU control signal to be supplied to the CPU 1, a peripheral circuit of the CPU 1, and a direct memory access (hereinafter referred to as DMA).
The peripheral circuits 3a and 3b which can operate are provided. The operating speed of the external circuit 9 is slower than the operating speed of the CPU 1.

The CPU 1, peripheral circuits 3a and 3b, address latch circuit 4, data latch circuit 5, and control circuit 6 are
It is formed by one chip. Further, the CPU 1 is connected to the address bus 7, the address bus 7 is connected to the external circuit 9 via the address latch circuit 4, and the CPU 1
Is connected to the peripheral circuits 3a and 3b and the data latch circuit 5 via the data bus 8, and the data latch circuit 5 is connected to the external circuit 9
Connected with.

The control circuit 6 is constructed as shown in FIG. That is, the output side of the decoder 10 to which the address sent by the CPU 1 is supplied is connected to the reset terminal of the flip-flop circuit 11. The decoder 10 is shown in FIG.
As shown in, when the CPU 1 supplies an address for the CPU 1 to access the external circuit 9, it is high.
When the (H) level signal is sent and the CPU 1 sends an address for accessing circuits other than the external circuit 9, it is low.
Sends an (L) level signal. Flip-flop circuit 1
1 indicates that when the decoder 10 sends an L level signal,
That is, it is reset when the CPU 1 does not access the external circuit 9.

The inverting output terminal of the flip-flop circuit 11 is connected to the data input terminal of the flip-flop circuit 11, the data input terminal of the next-stage flip-flop circuit 12, and one input terminal of the two-input AND circuit 13, and the flip-flop circuit 11 is connected. The output terminal of the circuit 12 is connected to the other input terminal of the AND circuit 13. Also, each flip-flop circuit 1
A clock signal supplied to the CPU 1 is supplied to 1 and 12.

Therefore, the AND circuit 13 operates when the flip-flop circuit 11 is not reset, that is, the CPU 1
L for instructing the latch of the address transmitted by the CPU 1 when the CPU 1 is transmitting the address for accessing the external circuit 9.
A level latch signal is sent to the address latch circuit 4. Therefore, the address latch circuit 4 latches the address sent from the CPU 1 to the external circuit 9.

The inverting output terminal of the flip-flop circuit 11 and the output terminal of the flip-flop circuit 12 are connected to the multiplexer 14. The multiplexer 14 is C
When writing data from PU1 to external circuit 9, CP
The output signal sent by the flip-flop circuit 12 is selected by the write signal sent by U1, and the external circuit 9 outputs C
The inverted output signal transmitted by the flip-flop circuit 11 is selected by the read signal transmitted by the CPU 1 when the data is read into the PU 1, and the L-level WAIT is selected.
It is sent to the CPU 1 as a signal. When the WAIT signal is supplied, the CPU 1 is placed in a wait state.

Further, the inverting output terminal of the flip-flop circuit 11 is connected to the other input terminal of the NOR circuit 15a to which the clock signal supplied to the CPU 1 is supplied to one input terminal, and the output terminal of the flip-flop circuit 12 is , C
The clock signal supplied to PU1 is connected to the other input terminal of the NOR circuit 15b supplied to one input terminal. Output sides of the NOR circuits 15a and 15b are connected to the multiplexer 16. The multiplexer 16 is supplied with the write signal to cause the flip-flop circuit 1 to operate.
1 outputs the inverted output signal, and when the read signal is supplied, the flip-flop circuit 12 selects the output signal and outputs the H-level data latch signal to the data latch circuit 5. Therefore, the data latch circuit 5 latches the data transmitted from the data bus 8 to the external circuit 9 and the data transmitted from the external circuit 9 to the data bus 8 in response to the supply of the data latch signal.

The operation of the access control circuit device configured as described above will be described below. As shown in (a) and (b) of FIG. 3, the CPU from the time t2 to the time t7 of the clock signal.
Assuming that 1 transmits an address n for accessing the external circuit 9 via the address bus 7 and the address latch circuit 4, the decoder 10 shown in FIG. As shown, the H level signal is sent to the reset terminal of the flip-flop circuit 11 while the address n is being sent.

Therefore, the control circuit 6 is synchronized with the change of the clock signal supplied to the CPU 1 by the operation of the flip-flop circuits 11 and 12 and the logical operation of the AND circuit 13, as shown in FIG. From time t3 to time t6 L
A level address latch signal is sent to the address latch circuit 4. Therefore, the address latch circuit 4 latches the address n sent by the CPU 1 when the address latch signal is supplied.

Now, it is assumed that the CPU 1 is performing a read operation for reading the data supplied from the external circuit 9. In such a case, the control circuit 6 receives the H supplied from the CPU 1.
When the level read signal is supplied to the multiplexer 14, the multiplexer 14 causes the flip-flop circuit 11 to operate.
Select the signal sent from the inverting output terminal of
As shown in (g), the L-level WAIT signal is sent to the CPU 1 from the time t3 to the time t5. Therefore, C
PU1 is in the wait state from time t3 to time t5, and releases address bus 7 and data bus 8.
Even during the period from time t3 to time t5, the address n is sent from the address latch circuit 4 to the external circuit 9, and the external circuit 9 executes the operation based on the address n.

On the other hand, since the address bus 7 and the like are released during the period from the time t3 to the time t5, the peripheral circuits 3a and 3b.
Can perform the DMA operation during the period from time t3 to time t5.

The control circuit 6 operates at the time t3 by the logical operation of the OR circuits 15a and 15b and the operation of the multiplexer 16.
After the wait state of the CPU 1 ends in the period from time t5 to time t5, as shown in (e) of FIG.
The data latch signal is sent to the data latch circuit 5 for the period of 6. Therefore, the data sent from the external circuit 9 is latched by the data latch circuit 5 and the wait state is released.
Data is taken into PU1.

Next, a case where the CPU 1 is performing a write operation for writing data to the external circuit 9 will be described. In such a case, the control circuit 6 first sets the OR circuits 15a and 15b.
3 and the operation of the multiplexer 16.
As shown in (f), the data latch signal is sent to the data latch circuit 5 from the time t3 to the time t4. Therefore, C
The data sent by PU1 is latched by the data latch circuit 5 and sent to the external circuit 9.

Next, the control circuit 6 selects the signal sent from the output terminal of the flip-flop circuit 12 by the multiplexer 14 by supplying the H-level write signal supplied from the CPU 1 to the multiplexer 14, and FIG. of
As shown in (h), the L-level WAIT signal is sent to the CPU 1 from the time t4 to the time t6. Therefore, C
PU1 is in the wait state from time t4 to time t6, and releases address bus 7 and data bus 8.
Note that the address n is sent from the address latch circuit 4 to the external circuit 9 even during the period from time t4 to time t6, and the external circuit 9 executes the operation based on the address n.

On the other hand, since the address bus 7 and the like are released during the period from time t4 to time t6, the peripheral circuits 3a and 3b.
Can perform the DMA operation during the period from time t4 to time t6.

In this way, in the transmission of the address and the data between the CPU 1 and the external circuit 9, the latch circuits for latching the address and the data are respectively provided to control the transmission timing of the address and the data. In other words, for example, Since the timing of supplying data from the external circuit 9 to the data bus 8 is controlled, when the CPU 1 is in the wait state, the peripheral circuit 3a is utilized by utilizing that period.
A DMA operation can be performed between equal parts, and after the DMA operation is completed, data is transmitted from the data latch circuit 5 to the CPU 1. Therefore, the processing speed of the entire system can be improved.

Second Embodiment: A second embodiment of the access control circuit device of the present invention will be described below with reference to FIG. In FIG. 4, the same components as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Second
In this embodiment, CPU1 is different from the first embodiment described above.
A CPU clock signal generation circuit 2 for generating a CPU clock signal, which is a CPU control signal, is provided from the clock signal, and the control circuit 6 is not provided.
These are the differences between the first embodiment and the second embodiment. In the second embodiment, the clock signal of the entire system is simply called the clock signal, and the clock signal supplied to the CPU 1 is called the CPU clock signal.

The CPU clock signal generation circuit 2 is constructed as shown in FIG. That is, the output side of the decoder 20 to which the address sent by the CPU 1 is supplied is connected to the data input terminal of the flip-flop circuit 21, the reset terminal of the flip-flop circuit 22, and one input side of the AND circuit 28. The output side of the flip-flop circuit 21 is feedback-connected to the input side, and the NAND circuits 23 and 24 are connected.
The output side of the flip-flop circuit 22 is connected to the multiplexer 26 via the NAND circuit 25 or directly.
Further, the output side of the NAND circuit 23 is an inverter 2 which sends an address latch signal to the address latch 4 shown in FIG.
9 is connected.

The multiplexer 26 selects the output signal of the NAND circuit 25 according to the read signal sent from the CPU 1, and selects the output signal of the flip-flop circuit 22 according to the write signal. The output side of the multiplexer 26 is a NOR whose clock signal is supplied to one input terminal.
It is connected to the other input terminal of the circuit 27, and the output side of the NOR circuit 27 is connected to the clock signal input terminal of the CPU 1 and the other input terminal of the AND circuit 28. The AND circuit 28 is a circuit for sending a data latch signal to the data latch circuit 5 shown in FIG.

The operation of the access control circuit device according to the second embodiment thus constructed will be described below with reference to FIG. Similar to the operation in the first embodiment, the CPU 1
The address n for accessing the external circuit 9 is transmitted during the period from time t2 to time t7. Therefore, CPU
During the period from time t2 to time t7 from the decoder 20 constituting the clock signal generation circuit 2, an H level signal is supplied to the reset terminal of the flip-flop circuit 22, and the flip-flop circuit 22 is not reset from time t2 to time t7. , The signal of the L level is changed from the time t4 to the time t6 by the supplied clock signal as shown in (g) of FIG.
It is sent to the ND circuit 25.

Further, the flip-flop circuit 21 is also supplied with the clock signal supplied thereto through the NAND circuit 23 as shown in FIG.
The signal as shown in (f) of is transmitted. Therefore, NAND
Due to the logical operation of the circuits 24 and 25, the NAND circuit 25
As shown in (h) of FIG. 6, a period L from time t2 to time t4
The level signal is sent to the multiplexer 26. The output side "A" of the NAND circuit 23 shown in FIG. 5 is (f) in FIG.
6A, the output side “B” of the flip-flop circuit 22 corresponds to the “B” shown in FIG. 6G, and the output side “C” of the NAND circuit 25 corresponds to the “A” shown in FIG. ) Corresponds to "C".

In the multiplexer 26, when the CPU 1 is sending the read signal, the NAND circuit 25 sends the signal shown in FIG. 6 (h), and when the CPU 1 is sending the write signal. The signal shown in (g) of FIG. 6 transmitted by the flip-flop circuit 22 is selected.
Therefore, the NOR circuit 27, to which the clock signal shown in FIG. 6 (a) is supplied, by the logical operation of the signal shown in FIG. 6 (g) and the clock signal when the CPU 1 is sending the write signal, As shown in (b) of FIG. 6, from time t5 to time 6, a CPU clock signal having no H level signal is sent to the CPU1, while when the CPU1 is sending a read signal, (h) of FIG. 6) and the clock signal, the CPU clock signal having no H level signal is sent to the CPU 1 from time t3 to time 4 as shown in FIG. 6C.

Therefore, when the CPU 1 is executing the write operation, as shown in (b) of FIG.
It means that the operation is stopped until 6 and when the read operation is executed, the operation is stopped from time t3 to time t4 as shown in (c) of FIG. It will be.

The address latch signal supplied to the address latch circuit 4 is sent from the inverter 29 shown in FIG. 5, and this address latch signal is a signal obtained by inverting the signal shown in FIG. And changes as shown in FIG. 6 (i). The data latch signal supplied to the data latch circuit 5 is sent from the AND circuit 28 shown in FIG.
When 1 is performing the write operation, the signal becomes the signal shown in (j) of FIG. 6, and when the CPU 1 is performing the read operation, the signal becomes the signal shown in (k) of FIG.

In this way, the CPU clock signal generation circuit 2
The address latch signal and the data latch signal sent to the address latch circuit 4 and the data latch circuit 5 are sent in the same manner as in the first embodiment at the timing described in the first embodiment. It is assumed that the times shown in FIGS. 3 and 6 are the same.

Therefore, as shown in FIG. 6, when the CPU 1 is executing the write operation, the peripheral circuit 3a or the like can perform the DMA operation from time t4 to time t6 corresponding to the operation stop period of the CPU 1. While the CPU 1 is executing the read operation, the peripheral circuit 3a and the like can perform the DMA operation from time t3 to time t5 corresponding to the operation stop period of the CPU 1.

As described above, in the first embodiment, the wait signal is supplied to the CPU 1 to stop the operation of the CPU 1.
In the second embodiment, the CPU clock signal supplied to the CPU 1 is thinned out to stop the operation of the CPU 1, so that the same effect as that described in the first embodiment can be obtained in the second embodiment. .

[0033]

As described in detail above, according to the present invention, C
By controlling the CPU operation by the PU control signal and controlling the timing of information transmission between the CPU and another semiconductor integrated circuit device, when the CPU is in a wait state, for example, another semiconductor integrated circuit Data transmission from the device to the CPU is stopped, and the DMA operation between the peripheral circuits can be performed safely.
Even when the semiconductor integrated circuit device accesses another semiconductor integrated circuit device, it can operate at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an access control circuit device of the present invention.

FIG. 2 is a logic circuit diagram showing an example of a configuration of a control circuit shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the access control circuit device shown in FIG.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the access control circuit device of the present invention.

5 is a logic circuit diagram showing an example of a configuration of a CPU clock signal generation circuit shown in FIG.

6 is a timing chart for explaining the operation of the access control circuit device shown in FIG.

FIG. 7 is a timing chart for explaining an operation when one semiconductor integrated circuit device accesses another semiconductor integrated circuit device.

[Explanation of symbols]

1 ... CPU, 2 ... CPU clock signal generation circuit, 3a, 3
b ... Peripheral circuit, 4 ... Address latch circuit, 5 ... Data latch circuit, 6 ... Control circuit, 7 ... Address bus, 8 ... Data bus, 9 ... External circuit.

Claims (3)

[Claims] 1. A direct memory having a central processing unit connected to an address bus and a data bus and a peripheral circuit of the central processing unit, the direct memory between the peripheral circuits when the central processing unit is in a wait state. An access control circuit device for controlling an access operation between a semiconductor integrated circuit device that performs an access operation and another semiconductor integrated circuit device different from the semiconductor integrated circuit device, the address bus and the data bus, and the other Information transmission control means connected between the central processing unit and the central processing unit for controlling address and data transmission between the central processing unit and the other semiconductor integrated circuit device, and the central processing unit. When another semiconductor integrated circuit device is accessed, a CPU control signal is sent to the central processing unit, and And a control means for sending a control signal for the transmission control to the transmission control unit,
An access control circuit device comprising: 2. The access control circuit device according to claim 1, wherein the CPU control signal is a wait signal for temporarily stopping an arithmetic operation in the central processing unit. 3. The access control circuit device according to claim 1, wherein the CPU control signal is a CPU clock signal supplied to a central processing unit.