JP2884620B2 - Digital image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing apparatus, and more particularly, to a digital image processing apparatus that performs a bit array inversion process of digital image data (hereinafter, simply referred to as image data) by hardware. .

[Conventional technology]

Conventionally, in this type of digital image processing apparatus, the bit arrangement inversion processing of image data is performed by an image processor reading image data to be processed from an image memory into a register in the image processor, and executing a command such as data shift. This has been realized by performing a bit array inversion process and writing the processed data to an image memory.

[Problems to be solved by the invention]

In the above-described conventional digital image processing apparatus, since the image processor performs the bit array inversion processing of the image data, the entire processing steps including other image processing are increased, and the time required for the image processing is increased. Has the disadvantage of being longer.

In view of the above, an object of the present invention is to provide a bit arrangement inversion circuit for performing a bit arrangement inversion process of image data during a read / write operation cycle of an image processor, thereby reducing an image processing step in the image processor. To provide a digital image processing apparatus capable of reducing the time required for image processing.

[Means for solving the problem]

A digital image processing apparatus according to the present invention detects an operation mode holding circuit for holding an operation mode having first to fourth set values set by a host device, and detects a read / write operation of an image memory of an image processor. When the operation mode held in the operation mode holding circuit is the first set value and the image processor performs a read operation, the output data of the image memory remains unprocessed during the read operation cycle of the image processor. When the operation mode held by the operation mode holding circuit is the first set value and the image processing processor is in the write operation, the output data of the image processing processor is not processed and the write operation cycle of the image processor is output to the data bus. During the operation, the data is output to the data bus on the image memory side, and the operation held in the operation mode holding circuit is performed. When the read mode is set to the second mode and the image processor performs a read operation, the output data of the image memory is output to the image processor side data bus during the read operation cycle of the image processor without processing, and the operation mode holding circuit When the operation mode held in the image processor is a write operation with the second set value, the output data of the image processor is subjected to bit array inversion processing and output to the image memory side data bus during the write operation cycle of the image processor. When the operation mode held by the operation mode holding circuit is the third set value and the image processing processor performs a read operation, the output data of the image memory is subjected to bit array inversion processing and the image processing is performed during the read operation cycle of the image processing processor. Output to the data bus on the processor side,
When the operation mode held by the operation mode holding circuit is the third set value and the image processor performs a write operation, the output data of the image processor remains unprocessed during the write operation cycle of the image processor. When the operation mode held in the operation mode holding circuit is the fourth set value and the image processing processor performs a read operation, the output data of the image memory is subjected to bit array inversion processing and the read operation cycle of the image processing processor is performed. During the operation, the operation mode is output to the data bus on the image processor side, and the operation mode held in the operation mode holding circuit is the fourth mode.
And a bit array inverting circuit for performing bit array inversion processing of output data of the image processor when the image processor performs a write operation at the set value and outputting the data to the image memory side data bus during a write operation cycle of the image processor.

[Action]

In the digital image processing apparatus according to the present invention, the operation mode holding circuit holds the operation modes taking the first to fourth set values set by the host device, and the bit array inversion circuit reads the image memory of the image processor. During the read operation cycle of the image processing processor, the output mode of the image memory is unprocessed when the image processing processor performs the read operation when the operation mode held in the operation mode holding circuit is the first set value and the write mode is detected. When the operation mode held in the operation mode holding circuit is the first set value and the image processing processor performs a write operation, the output data of the image processing processor is not processed and the image processing processor outputs the data to the image processing processor side data bus. Is output to the image memory side data bus during the write operation cycle of When the operation mode is the second set value and the image processor is in the read operation, the read operation of the image processor is output to the image processor side data bus during the cycle while the output data of the image memory is not processed, and the operation mode is retained. When the operation mode held in the circuit is the second set value and the image processor performs a write operation, the output data of the image processor is subjected to bit array inversion processing, and the data is transferred to the image memory side data bus during the write operation cycle of the image processor. When the operation mode held in the operation mode holding circuit is the third set value and the image processing processor performs a read operation, the output data of the image memory is subjected to bit array inversion processing and the image processing is performed during the read operation cycle of the image processing processor. Output to the data bus on the processing processor side and held in the operation mode holding circuit When the operation mode is the third set value and the image processor is in the write operation, the output data of the image processor is output unprocessed to the image memory side data bus during the write operation cycle of the image processor, and the operation mode holding circuit When the operation mode held in the image processor is a read operation with the fourth set value, the output data of the image memory is subjected to bit array inversion processing and output to the image processor side data bus during the read operation cycle of the image processor. When the operation mode held by the operation mode holding circuit is the fourth set value and the image processor performs a write operation, the output data of the image processor is subjected to bit array inversion processing and the image is processed during the write operation cycle of the image processor. Output to the memory side data bus.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital image processing apparatus according to one embodiment of the present invention. The main part of the digital image processing apparatus according to the present embodiment includes an operation mode holding circuit 2, an image processor 3, a bit array inverting circuit 4, and an image memory 5.

The operation mode holding circuit 2 is connected to the host device 1 via the signal line 6 and holds a set value of the operation mode set from the host device 1.

The image processor 3 is connected to the bit array inverting circuit 4 via the image processor-side data bus 7 and is connected to an image memory read / write controller signal line 9.
Are connected to the bit arrangement inverting circuit 4 and the image memory 5 via the.

The bit array inverting circuit 4 is connected to the image processor 3 via the image processor-side data bus 7 and to the image memory 5 via the image memory-side data bus 8. In addition, the bit arrangement inversion circuit 4
Are connected to the image processor 3 via the image memory read / write control signal line 9 and to the operation mode holding circuit 10 via the operation mode designation signal line 10.

The image memory 5 is connected to the bit array inversion circuit 4 via the image memory side data bus 8 and to the image processor 3 via the image memory read / write control signal line 9.

FIG. 2 shows the set values of the operation mode set in the operation mode holding circuit 2, the read / write operation of the image processor 5 with respect to the image memory 5, and the bit arrangement inversion circuit 4.
FIG. 4 is a table showing the relationship with the operation of FIG.

FIG. 3 is a circuit block diagram showing an example of the configuration of the bit array inversion circuit 4 that satisfies the relationship shown in FIG.
The bit arrangement inversion circuit 4 includes four data buffers 40
1 to 404, a data buffer control unit 410, four data buffer control signal lines 421 to 424, and two data bus bit array inversion connection modules 431 and 432.

The data buffer 401 has an input side connected to the image processor side data bus 7 and an output side connected to the image memory side data bus 8.
Connected to the data buffer control signal line 421
Is connected to the data buffer control unit 410 via the.

The data buffer 402 has an input side connected to the image memory side data bus 8 and an output side connected to the image processor side data bus 7.
Connected to the data buffer control signal line 422.
Is connected to the data buffer control unit 410 via the.

The data buffer 403 has an input side connected to the image processor side data bus 7, and an output side connected to the image memory side data bus 8 via the data bus bit array inversion connection module 431.
Connected to the data buffer control signal line 423
Is connected to the data buffer control unit 410 via the.

The data buffer 404 has an input side connected to the image memory side data bus 8 and an output side connected to the image processor side data bus 7 via the data bus bit array inversion connection module 432.
Connected to the data buffer control signal line 424
Is connected to the data buffer control unit 410 via the.

The data buffer control unit 410 is connected to the image memory read / write control signal line 9 and the operation mode designation signal line 10 and inputs a read / write signal to the image memory 5 of the image processor 3 and an operation mode set value. Data buffer control signal line according to the pattern of the input signal.
The data buffers 401 to 404 are controlled through 421 to 424.

Data bus bit array inversion connection module 431 and 4
Numeral 32 denotes an input-side data bus and an output-side data bus in which the bit arrangement is inverted.

Next, the operation of the digital image processing apparatus according to the present embodiment thus configured will be described.

The host device 1 sets the operation mode setting value in the operation mode holding circuit 2 via the signal line 6.

The operation mode holding circuit 2 holds the set value of the operation mode set by the host device 1 until the next set value of the operation mode is set, and sets the bit arrangement inversion circuit 4 via the operation mode designation signal line 10. Output the set value of the operation mode.

The image processor 3 controls the image memory 5 via the image memory read / write control signal line 9 and performs read / write access to the image memory 5 via the image processor-side data bus 7.

Then, the bit array inversion circuit 4 detects via the image memory read / write control signal line 9 whether the operation of accessing the image memory 5 by the image processor 3 is read or write, and the detected access of the image processor 3 is performed. According to the operation mode setting value input from the operation mode holding circuit 2 via the operation and operation mode designating signal line 10, the second
According to the relationship shown in the figure, the data input from the image processor-side data bus 7 or the image memory-side data bus 8 is subjected to bit array inversion processing or unprocessed, and the image processor-side data bus 7 or image memory is not processed. Output to the side data bus 8.

For example, the bit array inversion circuit 4 shown in FIG. 3 will be described in detail. When the operation mode set value is 1 and the image processor 3 performs a read operation, the data buffer control unit 410 The data buffer 402 is activated through 422 to output the output data of the image memory 5 on the image memory side data bus 8 to the image processor side data bus 7 without processing.

When the set value of the operation mode is 1 and the image processor 3 performs the write operation, the data buffer control unit 410 activates the data buffer 401 through the data buffer control signal line 421 and sets the data bus 7 on the image processor side.
The output data of the above image processor 3 is output to the image memory side data bus 8 without processing.

When the set value of the operation mode is 2 and the image processor 3 performs a read operation, the data buffer control unit 410 activates the data buffer 402 through the data buffer control signal line 422 and sets the image memory 5 on the image memory side data bus 8. Is output to the image processor side data bus 7 without processing.

When the set value of the operation mode is 2 and the image processor 3 performs the write operation, the data buffer control unit 410 activates the data buffer 403 through the data buffer control signal line 423 and the data bus 7 on the image processor side.
The output data of the above image processor 3 is subjected to bit array inversion processing through the data bus bit array inversion connection module 431 and output to the image memory side data bus 8.

When the set value of the operation mode is 3 and the image processor 3 performs a read operation, the data buffer control unit 410 activates the data buffer 404 through the data buffer control signal line 424 and sets the image memory 5 on the image memory side data bus 8. Is output through the data bus bit array inversion connection module 432 and output to the image processor side data bus 7.

When the set value of the operation mode is 3 and the image processor 3 performs the write operation, the data buffer control unit 410 activates the data buffer 401 through the data buffer control signal line 421 and
The output data of the above image processor 3 is output to the image memory side data bus 8 without processing.

When the set value of the operation mode is 4 and the image processor 3 performs a read operation, the data buffer control unit 410 activates the data buffer 404 through the data buffer control signal line 424 and activates the image memory 5 on the image memory side data bus 8. Is output through the data bus bit array inversion connection module 432 and output to the image processor side data bus 7.

When the set value of the operation mode is 4 and the image processor 3 performs a write operation, the data buffer control unit 410 activates the data buffer 403 through the data buffer control signal line 423 and sets the image processor-side data bus 7
The output data of the above image processor 3 is subjected to bit array inversion processing through the data bus bit array inversion connection module 431 and output to the image memory side data bus 8.

As a result, by the read / write access of the image processor 3, the bit array inversion processing of the image data is performed or not performed by the bit array inversion circuit 4, and the read / write operation to the image memory 5 is performed. .

〔The invention's effect〕

As described above, according to the present invention, by providing the bit array inversion circuit for performing the bit array inversion processing of the image data during the read / write operation cycle of the image processor, the bit array inversion processing of the image data is performed by hardware. This can reduce the number of image processing steps in the image processing processor, thereby shortening the image processing time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a digital image processing apparatus according to one embodiment of the present invention, and FIG. 2 is a diagram showing operation mode set values and reading of an image processor from an image memory in the digital image processing apparatus of this embodiment. FIG. 3 is a table showing the relationship between the / write operation and the operation of the bit array inverting circuit. FIG. 3 is a circuit block showing an example of the configuration of the bit array inverting circuit in FIG. In the figure, 1 ... host device, 2 ... operation mode holding circuit, 3 ... image processing processor, 4 ... bit array inversion circuit, 5 ... image memory, 6 ... signal line, 7 ... image processor 8: Image memory side data bus, 9: Image memory read / write control signal line, 10: Operation mode designation signal line, 401 to 404: Data buffer, 410: Data buffer control unit, 421 to 424: Data buffer control signal lines, 431, 432: Data bus bit array inversion connection modules.

Claims (1)

(57) [Claims] 1. A digital image processing device comprising an image processor and an image memory, comprising: an operation mode holding circuit for holding an operation mode taking first to fourth set values set by a host device; The read / write operation of the image memory is detected, the operation mode held in the operation mode holding circuit is the first set value, and when the image processor is in the read operation, the output data of the image memory is not processed and the image processing is performed. During the read operation cycle of the processor, the data is output to the data bus on the image processor side, and when the operation mode held in the operation mode holding circuit is the first set value and the image processor is in the write operation, the output data of the image processor is output. The data bus on the image memory side during the write operation cycle of the image processor without processing Output, the operation mode holding circuit operation mode stored in the second
During the read operation of the image processor, the output data of the image memory is output unprocessed to the image processor-side data bus during the read operation cycle of the image processor when the image processor performs the read operation, and is held in the operation mode holding circuit. When the operation mode is the second set value and the image processor performs a write operation, the output data of the image processor is subjected to bit array inversion processing and output to the image memory side data bus during a write operation cycle of the image processor. When the operation mode held in the holding circuit is the third set value and the image processor performs a read operation, the output data of the image memory is subjected to bit array inversion processing, and the image processor side data bus is executed during the read operation cycle of the image processor. To the operation mode held in the operation mode holding circuit. When the image processing processor performs the write operation with the third set value, the output data of the image processing processor is output to the image memory side data bus during the write operation cycle of the image processing processor without being processed, and is held in the operation mode holding circuit. When the operation mode is the fourth set value and the image processor performs a read operation, the output data of the image memory is subjected to bit array inversion processing and output to the image processor side data bus during the read operation cycle of the image processor. When the operation mode held by the operation mode holding circuit is the fourth set value and the image processor performs a write operation, the output data of the image processor is subjected to bit array inversion processing and the image memory is written during the write operation cycle of the image processor. And a bit array inverting circuit for outputting to the side data bus. Digital image processing apparatus for.