JPH0325539A - Storage device - Google Patents

Abstract

PURPOSE:To shorten data transfer time by providing a signal line to show the fact that a data transfer instruction is under execution, a register to hold data red out from a transfer origin address under the execution of the data transfer instruction, and a control circuit to perform data transfer control in its own device before a processor completes data transfer. CONSTITUTION:The storage device 2 is comprised of a memory 21 in which the data is stored, the register 22 for data holding, the control circuit 23 to perform the control of the device, and a data buffer 24. Firstly, the processor 1 sends out the signal of the data transfer instruction under execution to an output line (d), and also, sends out the transfer origin address to an output line (e). The control circuit 23, when receiving the signal of the data transfer instruction under execution and a write instruction, sets the data buffer 24 at a non-output state, and also, controls the register 22 at an output state. The memory 21 receives the transfer origin address via an input line (h), and also, receives the data via an output line (j). Thereby, the data transfer time can be shortened.

Description

TECHNICAL FIELD The present invention relates to a storage device, and more particularly to data transfer control in a storage device connected to a processor.

BACKGROUND ART Conventionally, data transfer control in an information processing apparatus has been performed as follows. First, when a data transfer command is input, the processor outputs a transfer source address and reads data from the main memory. Next, the processor outputs the transfer destination address and the read data again and writes them into the main memory.

However, in the data transfer control in the conventional information processing device described above, the processor reads the data and outputs the same data again, so even if the transfer destination address is first issued using the bus protocol, the data transfer is not performed until the processor outputs the data. has the disadvantage that it takes a long time to complete the transfer because it has to wait for writing.

OBJECTS OF THE INVENTION The present invention has been made in order to solve the above-mentioned conventional drawbacks, and it is an object of the present invention to provide a storage device that can shorten data transfer time.

Structure of the Invention A storage device according to the present invention is a storage device including a memory that sends data from a predetermined address in response to an access from a host device, and a storage device that holds the data sent by the memory; It is characterized by comprising a write means for writing the data held in the holding means to another address in response to another access from the host device.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of main parts of an information processing device including a storage device according to an embodiment of the present invention. In the figure, 1 is a processor, and 2 is a main storage device which is a storage device according to an embodiment of the present invention.

The processor 1 accesses the storage device 2.

The storage device 2 includes a memory 21 in which data is stored, a register 22 for holding data, a control circuit 23 for controlling the inside of the device, and a data buffer 24.

Note that 3 is a system bus, and this system bus 3 includes a control line a5, an address line b, and a data line C.

Further, d is a control signal output line of the processor 1, e is an address output line of the processor 1, f is a data output line of the processor 1, g is a control signal output line of the main storage device 2, and h is a control signal output line of the processor 1.
is an address input line of the main memory device 2, and i is a data input/output line of the main memory device 2.

Furthermore, j is a data output line of the memory 21, k is a control line to the data buffer 24, and g is a control line to the register 22.

In such a structure, the following processing is executed in response to a data transfer command.

First, the processor 1 sends a signal indicating that a data transfer command is being executed and a read instruction to the output line d, and also sends a read instruction to the output line e.
Sends the forwarding address to. Signals during execution of a data transfer command and designation of read are transmitted to the main memory device 2 through a control line a in the system bus 3, and a transfer source address is transmitted through an address line b in the system bus 3, respectively.

Then, the memory 21 receives the transfer source address through the input line h, and outputs the accessed data to the input/output line j.

Further, when the control circuit 23 receives a signal indicating that a data transfer command is being executed and a read designation through the input line g, it puts the data buffer 24 into the output state through the control line k, and controls the register 22 into the data latch state through the control line g. do. As a result, the data output to the human output line j is sent to the data line C in the system bus 3 through the human output line 1, and is held in the register 22.

On the other hand, after outputting the transfer source address and waiting enough time to secure access time for the memory 21, the Blosser 1 outputs the transfer source address to the output line d without waiting for data transfer from the main memory.
A write instruction is output to output line e, and a transfer destination address is output to output line e. Then, the data is sent to the main memory device 2 again through the control line a1 and the address line b in the system bus 3, respectively.

When the control circuit 23 receives a signal indicating that a data transfer command is being executed and a write instruction through the input line g, it puts the data buffer 24 into a non-output state through the control line k, and controls the register 22 into an output state through the control line ρ. . As a result, the previously held data from the transfer source address is output to the human output line j.

The memory 21 receives the transfer destination address through the human power line h, and also receives data through the human power line j. Then, the data is written to the transfer destination address of the memory 21, and the data transfer process ends.

Note that the data sent to the data line C in the system bus 3 is sent to the processor 1 through the input/output line f. The processor 1 completes the first bus cycle, sends the data back to the human output line f, and completes the second bus cycle, but the data transfer process has already been completed in the main memory. Therefore, the main memory device 2 can be prepared for the next access by the processor 1.

In other words, the present invention provides a memory address in a storage device,
In other words, data transfer processing is achieved by providing a register that temporarily holds the output data from the transfer source address and writing that output data to another address in memory, that is, the transfer destination address. Data transfer time between the storage device and the processor can be omitted.

Effects of the Invention As explained above, the present invention provides a signal line indicating that a data transfer instruction is being executed, a register that holds data read from a transfer source address during execution of a data transfer instruction, and a system bus control line. By providing a control circuit in the storage device that is connected to the processor and controls the data transfer within the device itself before the processor finishes the data transfer, the data transfer time is shortened and the throughput of the entire data transfer process is improved. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an information processing device including a storage device according to an embodiment of the present invention. Explanation of symbols of main parts 1... Processor 21... Memory 22... Register 23... Control circuit 24... Data buffer

Claims (1)

[Claims] (1) A storage device including a memory that sends data from a predetermined address in response to an access from a host device, and a holding unit that holds data sent by the memory;
A storage device comprising: writing means for writing data held in the holding means to another address in response to another access from the host device.