JPS61292739A - Memory device - Google Patents

Abstract

PURPOSE:To inverse an LSB and an MSB at a high speed by providing a multiplexer which supplies data to a memory directly or with inversion of the LSB and the MSB and another multiplexer which outputs data directly or with inversion. CONSTITUTION:The data on a data bus 12 is written to a memory 10 at an address designated by an address bus 11. While a multiplexer which works with a selection signal S1 of a controller 3 switches selectively an input A to receive the data on the bus 12 as it is and an input B to receive an LSB and an MSB with inversion and writes them to the memory 10. In a read mode, a multiplexer 2 which works with a selection signal S2 switches selectively an output (1) to receive the data of the memory 10 as it is and an output (2) to receive the data with inversion of the LSB and MSB and outputs them to the bus 12.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory device, and more particularly, in a microcomputer system, data MS B (Mo
st 51gn1ficant Bit) and LSB (L
The present invention relates to a memory device that performs high-speed inversion of eastS1gn1ficantBit).

Prior art] The leftmost bit of data such as 1 word or 1 byte handled by a computer system is MSB (Most Significant Bit)
, the rightmost bit is called the LSB (least significant bit) (see Figure 3 (b)). When handling data (in this case, parallel data) in a microcomputer system, the data string is (a) LSB The system starting from and (b) MSB
There is a system starting from .

Some microcomputer systems have these (,)
There are many systems in which systems (b) and (b) are mixed; in other words, in a processor that connects multiple input/output devices, one handles data starting from the LSB and the other handles data starting from the MSB for each input/output device. The data input to the processor is mixed with those that handle (a) and (b).
) systems will be mixed. In system (a),
If the input data starts from the MSB, it needs to be converted to data starting from the LSB.

In the system (b), it is necessary to similarly convert data starting from the LSB to data starting from the MSB.

Conventionally, when performing an inversion operation of the LSB and MSB.

Data is inverted by creating a table using software and referring to the table. but,
In this method, processing is performed by software in units of bytes or units of words, so it takes a very long time for data with a large number of words. This is a fatal drawback in image processing that handles a large amount of data.

Purpose An object of the present invention is to eliminate such conventional drawbacks and to invert the LSB and MSB in a computer system.
It is an object of the present invention to provide a memory device that can be used at high speed and easily.

Configuration In order to achieve the above object, the memory device of the present invention provides a computer system that is connected to a plurality of input/output devices, and in which data start bits for each input/output device are both LSB and 1M5B. a memory means, and upon writing to or reading from the memory means,
The multiplexer has a part that inputs and outputs the data string as it is and a part that inverts the LSB and MSB of the data string and inputs and outputs the data string. The feature is that it is performed using part or all of the output device address.

Hereinafter, the configuration of the present invention will be explained in detail by way of examples.

FIG. 1 is a block diagram of the periphery of a memory device showing an embodiment of the present invention.

In FIG. 1, l is the first multiplexer and 2 is the second multiplexer.
3 is a multiplexer, and 3 is a controller.

10 is a memory, 11 is an address bus, 12 is a data bus, RD is a read command signal, WR is a write command signal, and arrows indicate the transfer direction of data and signals, respectively.

In FIG. 1, between the data bus 12 and the memory 10 on the input and output sides of the memory l.

Multiplexers 1 and 2 are provided. Multiplexer 1
is a multiplexer on the input side, and its input section is provided with an input side and a B input side, of which the data line on the B input side has the LSB and MSB inverted. Furthermore, the data line on the input side is connected as is without being inverted. moreover.

The multiplexer 1 is provided with a select terminal S, and a select signal S from the controller 3 is connected to this terminal S.
Connect 1. On the other hand, the multiplexer 2 is an output-side multiplexer, and has one output side and two output sides on the data output side of the memory 10, with the second output side inverting the LSB and MSB, and the first output side leaving the data unchanged. Connect with . A select signal S2 from the controller 3 is connected to the S terminal of the multiplexer 2. The address is connected via an address bus 11 and input to the memory 10 together with a write command signal WT and a read command signal RD.

First, if data with the MSB and LSH inverted is required, multiplexer 1 selects the B side and writes it to the memory. That is, when write data is input via the data bus 12, the controller 3 sends a select signal S1 to the multiplexer 1, activates the multiplexer 1, and selects the B side with the multiplexer 1, so that the data is divided into the LSB and MSB. is inverted and input. At the same time, a memory address to be written is input via the address bus 11, and written to the memory in synchronization with the input of the write command signal WR. On the other hand, when the read data is inverted and sent out, the multiplexer 2 selects the 2nd output side and reads it. That is, when an address to be read is input via the address bus 11 and a read command signal RD is input, data is read from the corresponding address in the memory.
At the same time, the multiplexer 2 is activated by the select signal S2 from the controller 3, and the 2nd output side is selected by the multiplexer 2, so that the read data is MS
B and LSB are inverted and output, and if the data as is is required, reverse the operation described above, select the A input side for the input data with multiplexer 1,
The data is written to the memory 10 by inputting the write command signal WR and the write address. Furthermore, when the multiplexer 2 selects the 1st output for the output data and the data is read from the memory 10 by inputting the read command signal RD and the read address, it is transferred to the data bus 12 via the multiplexer 2 in that state. Output. Furthermore, by controlling multiplexer 2 on the output side, the data that has been inverted once and stored in memory 10 can be freely converted to MS.
You can select data with B and LSB inverted or the data as is.

In this way, the operation of inverting the LSB and MSB and the operation of restoring the inverted data are automatically performed by simply writing or reading data into the memory 10. Moreover, the area of the memory 10 can be freely selected based on the address.

FIG. 2 is a configuration diagram of the controller shown in FIG. 1.

The controller 3 is composed of an address decoder 21, a latch circuit 22, and an AND'7' gate 23, as shown in FIG. The controller 3 is an input/output device (
Ilo).

Normally, a processor determines a unique address for an input/output device, and by specifying this address, it sends write commands and read commands to the input/output device, and exchanges data between the main memory and the input/output device. At this time, the output obtained by decoding the specified input/output address is logically ANDed with the write command, and the write side selects the read side based on the preset data, and the multiplexer 1
Alternatively, by sending select signals SL and S2 to 2, it is determined whether or not to invert the LSB and MSB. That is, the input/output device address "ADR" is decoded by the address decoder 21, and the IO write command is ANDed.
The latch circuit 22 leading to the gate 23 sends out a select signal S1 when it latches the data DO, and sends out a select signal S2 when it latches the data D1. When the address decoder 21 decodes the I10 address and this becomes the address of the controller, the GE multiplication signal rises, the I10 write command issued from the processor becomes valid, and is input to the latch circuit 22 through the AND gate 23. The data at that time is latched.

If the data is DO.

If the select signal S1 rises and the data is DI,
The select signal S2 rises, thereby activating multiplexer 1 or 2, and multiplexer 1 selects the input side or the input side B.

The multiplexer 2 selects the 1 output side or the 2 output side.

Effects As explained above, according to the present invention, the LSB of data
The inversion of MSH and MSH can be realized at extremely high speed and can be performed automatically using simple hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the peripheral portion of a memory device showing an embodiment of the present invention, FIG. 2 is a configuration diagram of the controller in FIG. 1, and FIG. 3 is an explanatory diagram of the inversion operation of LSB and MSH. l, 2: Multiplexer, 3: Controller, 10: Memory, 11 Near address bus, 12: Data bus, 21 Near address decoder, 22: Launch circuit, 23: AN
D gate.

Claims (2)

[Claims] (1) Connected to multiple input/output devices, and the data start bit for each input/output device is LSB, and M
In a computer system in which the start bit is LSB or MSB, there is a memory that stores a data string whose start bit is LSB or MSB, and a terminal that inputs the input data string to the memory as is, or a terminal that stores the data string whose start bit is LSB or MSB, or
A multiplexer that selects one of the terminals to input with B inverted, and a terminal that outputs the output data string from the memory as it is or a terminal that inverts the LSB and MSB and outputs them. A memory device comprising a multiplexer and a controller that selectively activates one of the multiplexers. (2) The above controller enables the input/output write command by decoding the input/output device address, latches the data set in advance by the input/output write command, and selects and activates the multiplexer according to the content of the data. 2. The memory device according to claim 1, wherein the memory device transmits a signal to cause