JPS6154288B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to provide a gain control circuit with high practical sensitivity.

FIG. 1 is a system block showing an AM radio receiving apparatus according to an embodiment of the present invention, in which 1 is an antenna, 1' is an interstage frequency selection element, 2 is an RF amplification stage, 3 is an interstage frequency selection element, and 4 is an antenna. is a frequency conversion stage, 5 is an interstage frequency selection element, 6 is a first intermediate frequency amplification stage, 7 is an interstage frequency selection element, 8 is a second intermediate frequency amplification stage, 9 is an audio and AGC detection stage, 10
is the audio amplification stage, 13 is the speaker, 14 is the AGC
17 is a voltage comparator, and 18 is a reference voltage source.

In addition, in the AM radio receiving apparatus according to this embodiment, as shown in FIG. and when the received radio wave intensity further increases, the RF to AGC voltage 12 is adjusted so that the gain 111 of the RF amplification stage 2 is reduced from c to d and further from e to f.
The gain control sensitivities of the amplification stage 2 and the first intermediate frequency amplification stage 6 are set respectively. In addition, when a signal with an even higher received radio wave intensity is received and the output signal of the RF amplification stage is about to clip, the voltage comparator 17 uses the reference value of the reference voltage source 18 and the amplitude value of the output signal of the RF amplification stage 2. A detection output signal 19 is generated by comparing the detection output signal 19 and the gain 111 of the first intermediate frequency amplification stage 6 and the gain 112 of the RF amplification stage 2 as shown in FIG. It is lowered as shown in e to f.

Specifically, as shown in FIG.
The detected output signal 19 of 7 is applied to the AGC filter 14, smoothed, and the gain of the first intermediate frequency amplification stage 6 and the RF amplification stage 2 is reduced through the normal AGC path.

Moreover, FIG. 3 is a circuit diagram showing an embodiment in which the system block shown in FIG. is formed. The numbers in circles indicate the pin numbers of the integrated circuit, and the circuit elements outside the broken lines electrically connected to these pins are all discrete components and constitute the external circuit network of the integrated circuit.

In these three figures, the radio waves received by antenna 1 are transmitted through capacitors C ₁₀₁ , C ₁₀₂ , C ₁₀₃ and coil L ₁₀₁
It is applied to pin 1 through an interstage frequency selection element consisting of. The RF signal applied to pin 1 is RF
The signal is amplified by a common-emitter transistor Q ₃ as an amplification transistor in the amplification stage, and a common-base transistor Q ₄ , and an RF output signal is obtained from pin 15. The emitter of the amplification transistor _Q3 is connected to the ground potential point, which is a reference potential point, via a resistor _R4 as an impedance means, and is connected to the emitter-coupled pair of transistors _Q4 and _Q5 in the collector of the amplification transistor _Q3 . . Note that an interstage frequency selection element consisting of a capacitor C ₁₀₆ and a coil L ₁₀₂ is connected to the 15th pin. In particular, this coil L ₁₀₂ serves as a collector load impedance for the emitter-coupled pair of transistors Q ₄ and Q ₅ and for Q ₄ . Further, the RF signal obtained from pin 15 is applied to pin 11 via capacitor C ₁₀₇ , and further applied to the base electrode of transistor Q ₂₀ in the frequency conversion stage. Transistors Q ₁₃ and Q ₁₉ constitute a local oscillator in the frequency conversion stage, and the local oscillation frequency is determined by external circuit elements L ₁₀₃ , C ₁₀₈ , and C ₁₀₉ connected to pins 12, 13, and 14. Within this frequency conversion stage, the RF signal and the local oscillator signal are frequency mixed and the intermediate frequency signal is
Obtained from the collector of Q ₁₉ , that is, pin 12. 12
The intermediate frequency signal obtained from the pin is transmitted through the first intermediate frequency transformer IFT1 and the capacitor _C110 .
The signal is applied to the pin, amplified by the amplification transistors Q ₂₁ and Q ₂₈ of the first intermediate frequency amplification stage, and taken out to the 9th pin. The intermediate frequency signal obtained from this 9 pin is transferred to the second intermediate frequency transformer IFT2, and the capacitor
It is applied to pin 8 via C ₁₁₁ and C ₁₁₂ , amplified by transistors Q ₂₉ and Q ₃₀ of the second intermediate frequency amplification stage, and applied to the base electrode of the detection transistor Q ₃₁ of the audio and AGC detection stage. The intermediate frequency signal is transmitted through the base and emitter of the detection transistor _Q31 ,
Resistor connected to the emitter of transistor Q ₃₁
AM detection is performed by R ₂₈ and capacitor C ₁₁₄ , and an audio signal is obtained from pin 6. Although not shown,
The sound is transmitted to the audio amplification stage and the speaker.

Also, the audio signal obtained from pin 6 is
It is smoothed by an AGC filter consisting of a resistor R ₂₉ connected to the pin, a capacitor C ₁₁₇ connected to the 4th and 5th pins, and an emitter follower circuit Q ₃₂ ,
From the emitter of transistor Q ₃₃ via Q ₃₃
AGC voltage can be obtained. PNP transistor Q ₃₄ and diode Q ₃₅ connected between pins 14 and 15,
The network constructed from Q ₃₆ constitutes a voltage comparator. The detection output signal of this voltage comparator is obtained from the collector of the PNP transistor Q ₃₄ and is applied to one end of the capacitor C ₁₁₇ that constitutes the AGC filter, that is, the 5th pin.

On the other hand, a voltage dividing resistor consisting of three resistors R ₃₁ , R ₃₂ , and R ₃₃ is connected between the emitter electrode of transistor Q ₃₃ and the ground potential point, and the RF for the common AGC voltage is connected.
The gain control sensitivities of the amplification stage and the first intermediate frequency amplification stage are set respectively, and the conductivity of the control transistor Q ₂₇ of the first intermediate frequency amplification stage changes with respect to an increase in received radio field strength, that is, an increase in AGC voltage. This reduces the conductivity of the variable current transistor Q ₂₅ and reduces the emitter current of the amplification transistors Q ₂₁ , Q ₂₂ , so that the diodes Q ₂₃ ,
The emitter current, which used to flow in large quantities in Q ₂₄ , decreases and now flows in resistors R ₁₉ and R ₂₀ , and the gain 112 of the first intermediate frequency amplification stage becomes as shown in Figure 2 a to b.
It decreases as follows. The details of the circuit operation are described in Japanese Patent Application No. 46-9349 (Japanese Unexamined Patent Publication No. 47-22655) entitled "Amplifier Circuit", so please refer to it. Furthermore, when the received radio wave intensity increases, the potential at the connection point of the voltage dividing resistors R ₃₁ and R ₃₂ as the first gain control signal increases, and the degree of conduction of the control transistor Q ₈ of the RF amplification stage increases. By the control transistor
The degree of conductivity of _Q7 begins to decrease, and the degree of conductivity of diode _Q6 , which is a circuit element with variable conductivity, also decreases. If the conductivity of the diode Q ₆ as a circuit element is extremely high, the emitter electrode of the amplification transistor Q ₃ in the RF amplification stage is AC grounded by the capacitor C ₁₀₅ connected to pin 3, so that the amplification transistor Q ₃ is set to a high gain state, but when the conductivity of the diode _Q6 , which is a circuit element with variable conductivity, decreases, this conduction resistance increases, and the gain of the amplification transistor _Q3 is determined by this conduction resistance and the emitter resistance _R4. and become dependent on
The gain 111 of the RF amplification stage decreases as shown in FIG. 2c to d. Furthermore, when the received radio wave intensity increases, the voltage at the connection point between the voltage dividing resistors R ₃₂ and R ₃₃ increases, and the collector potential of the control transistor Q ₁ of the RF amplification stage as the second gain connection signal decreases. Thus, when the collector potential of the control transistor Q ₁ as the second gain connection signal is high, the amplification transistor Q ₄ of the RF amplification stage is conductive and the amplification transistor Q ₅ is non-conductive, so that the amplification transistor Q ₃
Most of the RF signal current flowing through the amplification transistor
_Q4 , the RF amplification stage is set to a high gain state, but when the collector potential of control transistor _Q1 decreases, amplification transistor _Q4 becomes non-conductive, amplification transistor _Q5 becomes conductive, and the RF amplification stage The gain 111 decreases as shown in FIG. 2e to f.

Therefore, the gain of the RF amplification stage according to this embodiment is 11
1 is controlled in two stages as shown in FIG. 2 c to d and e to f, so that it is possible to obtain an RF amplifier circuit that is controlled from high gain to low gain and has high practical sensitivity.

That is, according to this embodiment of the present invention, the original objective can be achieved through the following effects.

(1) The control transistors Q ₇ and Q ₈ controlled by the first gain control signal control the circuit element Q ₆ to maximum conductivity, and the second gain control signal turns one transistor Q ₄ fully ON and the other transistor
When Q ₅ is completely OFF, one transistor
Q ₄ , amplifying transistor Q ₃ , circuit element Q ₆ with variable conductivity, and capacitor C ₁₀₅ cooperate to maximize the voltage gain of the gain control circuit.

Incidentally, in the embodiment of the present invention, the emitter of the amplification transistor _Q3 is AC grounded to the ground potential via the conductive circuit element _Q6 and the capacitor _C105 with small AC impedance. In response to the RF signal applied to the base of Q ₃ , a large-amplitude RF signal current is obtained from its collector, and the large-amplitude RF signal current obtained from the collector of amplification transistor Q ₃ is a completely ON state transistor.
Since the voltage is supplied to the coil L ₁₀₂ as a load through Q ₄ , the gain control circuit configured as an RF amplification stage performs amplification operation at the maximum voltage gain, and the impedance of the coil L ₁₀₂ as a load is increased to a large value. By setting the maximum voltage gain to , the value of this maximum voltage gain can be made extremely large. . Such amplification operation at the maximum voltage gain of the RF amplification stage is extremely effective when the received radio wave intensity is extremely low and the amplitude level of the RF signal from the antenna 1 is extremely small.

(2) When the circuit element Q ₆ is controlled to be non-conductive by the control transistors Q ₇ and Q ₈ controlled by the first gain control signal, and one transistor Q ₄ is controlled to be completely ON by the second gain control signal, The circuit element Q ₆ and the capacitor C ₁₀₅ no longer participate in the amplification operation, and the voltage gain of the gain control circuit becomes an intermediate value due to the amplification transistor Q ₃ and the impedance means R ₄ .

Incidentally, in the embodiment of the present invention, in response to the RF signal applied to the base of the amplification transistor _Q3 , its collector generates a medium-amplitude RF signal current inversely proportional to the resistance value of the resistor _R4 as an impedance. is obtained and supplied to the coil L ₁₀₂ as a load via the transistor Q ₄ which is in a fully ON state, so that the gain control circuit configured as an RF amplification stage performs an amplification operation with a voltage gain of an intermediate value. Such amplification operation of the RF amplification stage with a voltage gain of an intermediate value is extremely effective when the amplitude level of the RF signal at the antenna 1 is intermediate.

(3) Furthermore, when one transistor Q ₄ is almost completely turned off by the second gain control signal, the RF signal current in the collector of the amplification transistor Q ₃ becomes a load.
Almost no voltage is transmitted to L ₁₀₂ , and the voltage gain of the gain control circuit is minimized.

Incidentally, in the embodiment of the present invention, since the circuit element _Q8 is rendered non-conductive in this case, the collector of the amplification transistor _Q3 is connected by the resistor _R4 .
The RF signal current is not extremely large, and most of this collector RF signal current is caused by the load.
The current flows through the other transistor Q ₅ rather than through L ₁₀₂ , preventing a large voltage drop in response to the RF signal at load L ₁₀₂ from occurring. If such a large voltage drop occurs in the load L ₁₀₂ , the pair of transistors Q ₄ and amplification transistor Q ₃ will be driven into the saturation region, and the RF amplified output signal will have a more faithful waveform than the load L ₁₀₂ . I can't take it out. On the other hand, in this embodiment, since the occurrence of such a voltage drop or driving into the saturation region is reduced, the RF
When the amplitude level of the signal is extremely strong,
The RF amplification stage performs its amplification operation with minimal voltage gain, resulting in a more faithful waveform than the load _L102 .
It is extremely effective as it can extract the RF amplified output signal.

Thus, according to the present invention, the voltage gain of the gain control circuit can be controlled to an extremely large maximum value, an intermediate value, or an extremely small minimum value within a wide variation range.

On the other hand, in the low gain state the emitter has low resistance R ₄
Since the amplification transistor _Q3 operates with a low distortion factor, the input dynamic range can be increased.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing an AM radio receiving device according to an embodiment of the present invention, and FIG.
Regarding changes in received radio field strength of the receiving device shown in the figure
FIG. 3 is a circuit diagram showing an embodiment in which the system block shown in FIG. 1 is applied to a monolithic semiconductor integrated circuit. _Q3 ...Amplifying transistor, _Q4 , _Q5 ...Pair of transistors, _Q6 ...Circuit element with variable conductivity,
_Q7 ...control transistor, _R7 ...impedance means, _L102 ...load impedance means, gain control voltage generation circuit... _Q33 , _R31 , _R32 , _R33 .

Claims (1)

[Claims] 1 an amplification transistor Q ₃ having an emitter connected to a reference potential point via impedance means R ₄ and a base to which an input signal is applied; a pair of transistors Q ₄ having an emitter connected to the collector of the amplification transistor Q ₃ ; , Q ₅ , a load impedance L ₁₀₂ connected to the collector of one Q ₄ of the pair of transistors Q ₄ and Q ₅ , a circuit element Q ₆ whose conductivity can be varied, and a connection between the circuit element Q ₆ and the reference potential point. capacitor C ₁₀₅ connected between the first
It comprises a control transistor _Q7 controlled by a gain control signal, the circuit element _Q6 is connected to the amplification transistor _Q3 and the control transistor _Q7 , and the conductivity of the circuit element _Q6 is The circuit element Q controls the signal amplitude level appearing at the load impedance L ₁₀₂ in cooperation with the amplification transistor Q ₃ and the capacitor C ₁₀₅ and is controlled by _the first gain control signal. ₆ , the signal amplitude level generated at the load impedance L ₁₀₂ is lowered, and the base of one of the pair of transistors Q ₄ and Q ₅ , Q ₄ , is controlled by the second gain control signal. Gain control characterized by lowering the conductivity of one of the transistors _Q4 whose collector is connected to the load impedance _L102 , thereby further reducing the signal amplitude level generated at the load impedance _L102 . circuit.