JPS6252490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides the following advantages: When the amplitude level of the RF signal of the antenna is extremely small, or has an intermediate value,
It is an object of the present invention to provide a receiving device that is capable of receiving and reproducing operations even when the signal strength is extremely high.

FIG. 1 is a system block showing an AM radio receiving apparatus according to an embodiment of the present invention, in which 1 is an antenna, 1' is an inter-stage frequency selection element, 2 is an RF amplification stage, 3 is an inter-stage frequency selection element, 4 is a frequency conversion stage, 5 is an interstage frequency selection element, 6 is a first intermediate frequency amplification stage, 7 is an interstage frequency selection element, 8 is a second intermediate frequency amplification stage, 9 is an audio and AGC detection stage, 10
is the audio amplification stage, 13 is the speaker, 14 is the AGC
17 is a voltage comparator, and 18 is a reference voltage source.

In addition, in the AM radio receiving apparatus according to this embodiment, as shown in FIG. The RF amplification stage 2 and the first intermediate frequency amplification for the AGC voltage 12 are configured such that the gain 111 of the RF amplification stage 2 is further reduced from e to d and further from e to f when the received radio wave intensity increases. The gain control sensitivities of stages 6 are each set. Furthermore, when a signal with an even higher reception radio field intensity is received and the output signal of the RF amplification stage is about to clip, the voltage comparator 17 compares the reference value of the reference voltage source 18 with the amplitude of the output signal of the RF amplification stage 2. A detected output signal 19 is generated by comparing the detected output signal 19, and the detected output signal 19 determines the gain 111 of the first intermediate frequency amplification stage 6 and the gain 112 of the RF amplification stage 2 as shown in FIGS. , e to f.

Specifically, as shown in FIG.
The detected output signal 19 is applied to the AGC filter 14, smoothed, and the gains of the first intermediate frequency amplification stage 6 and the RF amplification stage 2 are reduced through the normal AGC path.

Moreover, FIG. 3 is a circuit diagram showing an embodiment in which the system block shown in FIG. is formed. The numbers in circles indicate the pin numbers of the integrated circuit, and the circuit elements outside the broken lines electrically connected to these pins are all discrete components and constitute the external circuit network of the integrated circuit.

In Fig. 3, the radio waves received by antenna 1 are transmitted through capacitors C ₁₀₁ , C ₁₀₂ , C ₁₀₃ and coil
It is applied to pin 1 via an interstage frequency selection element consisting of _L101 . The RF signal applied to pin 1 is connected to a common emitter transistor in the RF amplification stage.
It is further amplified by Q ₃ and the common base transistor Q ₄ , and an RF output signal is obtained from pin 15. Note that an interstage frequency selection element consisting of a capacitor C ₁₀₆ and a coil L ₁₀₂ is connected to the 15th pin. Also, the RF signal obtained from pin 15 is connected to the capacitor.
It is applied to pin 11 via C ₁₀₇ and further to the base electrode of transistor Q ₂₀ in the frequency conversion stage. Transistors Q ₁₈ and Q ₁₉ constitute a local oscillator in the frequency conversion stage, whose local oscillation frequency is
Circuit element L ₁₀₃ externally attached to pins 12, 13, and 14,
Determined by C ₁₀₈ , C ₁₀₂ , and C ₁₀₉ . Within this frequency conversion stage, the RF signal and the local oscillation signal are frequency mixed and an intermediate frequency signal is obtained from the collector of transistor _Q19 , ie, pin 12. The intermediate frequency signal obtained from pin 12 is applied to pin 10 via the first intermediate frequency transformer IFT ₁ and capacitor C ₁₁₀ , and is amplified by the amplification transistors Q ₂₁ and Q ₂₈ of the first intermediate frequency amplification stage. It is taken out by the 9 pin. The intermediate frequency signal obtained from this 9 pin is transferred to the second intermediate frequency transformer IFT ₂ , capacitors C ₁₁₁ and C ₁₁₂
The signal is applied to pin 8 via , is amplified by transistors Q ₂₉ and Q ₃₀ of the second intermediate frequency amplification stage, and is applied to the base electrode of the detection transistor Q ₃₁ of the audio and AGC detection stage. The intermediate frequency signal is detected by the base and emitter of the detection transistor _Q31 .
Resistor R ₂₈ connected to the emitter of Q ₃₁ , capacitor
AM detection is performed by C ₁₁₄ , and an audio signal is obtained from pin 6, which is transmitted to an audio amplification stage and a speaker (not shown).

Also, the audio signal obtained from pin 6 is smoothed by an AGC filter consisting of a resistor R ₂₉ connected to pins 5 and 6 and a capacitor C ₁₁₇ connected to pins 4 and 5, and is smoothed by an emitter follower circuit Q ₃₂ , Q ₃₃
The AGC voltage is obtained from the emitter of transistor _Q33 . Connected between pins 14 and 15
A circuit network composed of a PNP transistor Q ₃₄ and diodes Q ₃₅ and Q ₃₆ constitutes a voltage comparator.
The detection output signal of this voltage comparator is obtained from the collector of the PNP transistor _Q34 , and is applied to one end of the capacitor _C117 constituting the AGC filter, that is, the 5th pin.

On the other hand, a voltage dividing resistor consisting of three resistors R ₃₁ , R ₃₂ , and R ₃₃ is connected between the emitter electrode of transistor Q ₃₃ and the ground potential point, and the RF for the common AGC voltage is connected.
The gain control sensitivities of the amplification stage and the first intermediate frequency amplification stage are set respectively, and the conductivity of the control transistor Q ₂₇ of the first intermediate frequency amplification stage changes with respect to an increase in received radio field strength, that is, an increase in AGC voltage. This reduces the conductivity of the variable current transistor Q ₂₅ and reduces the emitter current of the amplification transistors Q ₂₁ , Q ₂₂ , so that the diodes Q ₂₃ ,
The emitter current, which used to flow in large quantities through Q ₂₄ , decreases and now flows through resistors R ₁₉ and R ₂₀ , and the gain 112 of the first intermediate frequency amplification stage becomes as shown in Figure 2 a to b.
It decreases as follows. The details of the circuit operation are described in Japanese Patent Application No. 46-9349 (Japanese Unexamined Patent Publication No. 47-22655) entitled "Amplifier Circuit", so please refer to it. Furthermore, as the received radio wave strength increases, the voltage dividing resistor
The potential at the connection point of R ₃₁ and R ₃₂ increases, the conductivity of the control transistor Q ₈ of the RF amplification stage increases, and the conductivity of the control transistor Q ₇ decreases, causing the diode Q ₆ to decrease. The degree of conductivity also decreases. Thus, the conductivity of the diode Q6 is ₃ , and the emitter electrode of the amplification transistor _Q3 of the RF amplification stage is 3.
Since the capacitor C ₁₀₅ connected to the pin connects the amplification transistor Q 3 to AC ground, the amplification transistor Q ₃ is set to a high gain state, but when the conductivity of the diode Q ₆ decreases, this conduction resistance increases and the amplification transistor The gain of Q ₃ now depends on the emitter resistance R ₄ , and the gain 111 of the RF amplification stage is shown in Figure 2c.
It decreases from d to d. Furthermore, when the received radio wave intensity increases, the voltage at the connection point of the voltage dividing resistors R ₃₂ and R ₃₃ increases, and the control transistor Q ₁ of the RF amplification stage increases.
The collector potential of decreases. Thus, when the collector potential of control transistor _Q1 is high, RF
Since the amplification transistor Q ₄ in the amplification stage is conductive and the amplification transistor Q ₅ is non-conductive, most of the RF signal current flowing through the amplification transistor Q ₃ flows through the amplification transistor Q ₄ , and the RF amplification stage is set to a high gain state. However, when the collector potential of the control transistor Q ₁ decreases, the amplification transistor Q ₄ becomes non-conductive and the amplification transistor Q ₅ becomes conductive, and the gain 111 of the RF amplification stage decreases as shown in FIGS. 2e to 2f.

Therefore, the gain of the RF amplification stage according to this embodiment is 11
1 is controlled in two stages as shown in FIG. 2 c to d and e to f, so that it is possible to obtain an RF amplifier circuit that is controlled from high gain to low gain and has high practical sensitivity.

That is, according to this configuration of the present invention, the original purpose can be achieved by the following effects.

(1) When the amplitude level of the RF signal of antenna 1 is minute, the circuit element is
Q ₆ is controlled to maximum conductivity, one transistor Q ₄ is completely turned on and the other transistor Q ₅ is completely turned off by the second gain control signal, and one transistor Q ₄ , amplification transistor Q ₃ , and circuit element Q ₆ , capacitor C ₁₀₅ cooperate to maximize the voltage gain of the RF amplification stage.

Incidentally, in the embodiment of the present invention, the emitter of the amplification transistor _Q3 is AC grounded to the ground potential via the conductive circuit element _Q6 and the capacitor _C105 with small AC impedance. In response to the RF signal applied to the base of Q ₃ , a large-amplitude RF signal current is obtained from its collector, and the large-amplitude RF signal current obtained from the collector of amplification transistor Q ₃ is a completely ON state transistor.
Since the voltage is supplied to the coil L ₁₀₂ as a load through Q ₄ , the RF amplification stage performs amplification operation with maximum voltage gain, and the coil L ₁₀₂ as a load
By setting the impedance to a large value, the value of this maximum voltage gain can be made extremely large. Such amplification operation at the maximum voltage gain of the RF amplification stage is extremely effective when the received radio wave intensity is extremely low and the amplitude level of the RF signal from the antenna 1 is extremely small.

(2) When the amplitude of the RF signal of antenna 1 is an intermediate value, the circuit element is controlled by the first gain control signal.
Since Q ₆ is controlled to be non-conductive and one transistor Q ₄ is controlled to be completely ON by the second gain control signal, circuit element Q ₆ and capacitor C ₁₀₅ are no longer involved in the amplification operation, and the amplification transistor
Q ₃ and impedance means R ₄ give the voltage gain of the RF amplification stage an intermediate value.

Incidentally, in the embodiment of the present invention, in response to the RF signal applied to the base of the amplification transistor _Q3 , its collector generates a medium-amplitude RF signal current inversely proportional to the resistance value of the resistor _R4 as an impedance. is obtained and supplied to the coil L ₁₀₂ as a load via the transistor Q ₄ which is in a fully ON state, so the RF amplification stage performs an amplification operation with a voltage gain of an intermediate value. Such amplification operation of the RF amplification stage with a voltage gain of an intermediate value is extremely effective when the amplitude level of the RF signal at the antenna 1 is intermediate.

(3) When the amplitude of the RF signal from antenna 1 is extremely strong, the second gain control signal turns one transistor Q ₄ almost completely OFF, so that the RF signal current at the collector of amplification transistor Q ₃ increases to the load L. ₁₀₂ is almost no longer transmitted,
The voltage gain of the RF amplification stage is minimized.

Incidentally, in the embodiment of the present invention, since the circuit element _Q6 is rendered non-conductive in this case, the collector of the amplification transistor _Q3 is connected by the resistor _R4 .
The RF signal current also does not have an extremely large value, and most of the RF signal current of this collector flows not to the load L ₁₀₂ but to the other pair of transistors Q ₅ .
A large voltage drop in response to the RF signal at load L ₁₀₂ is prevented from occurring. If such a large voltage drop occurs in the load L ₁₀₂ , the pair of transistors Q ₄ and the amplification transistor Q ₃ will be driven into the saturation region, and the load L ₁₀₂ will be driven into the saturation region.
It becomes impossible to extract an RF amplified output signal with a more faithful waveform. On the other hand, in this embodiment, since the occurrence of such a voltage drop or driving into the saturation region is reduced, the RF
When the amplitude level of the signal is extremely strong,
Since the RF amplification stage performs its amplification operation with minimum voltage gain, the load _L102 provides a more faithful waveform of the RF
The amplified output signal can be extracted and is extremely effective.

Thus, according to the invention, the antenna's RF
When the amplitude level of the signal is minute, the voltage gain of the RF amplification stage reaches its maximum value, and the antenna's RF
If the signal amplitude level is intermediate,
The voltage gain of the RF amplification stage is an intermediate value, and if the amplitude level of the RF signal from the antenna is extremely strong, the voltage gain of the RF amplification stage is the minimum value. Reproduction operation can be made possible.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing an AM radio receiving device according to an embodiment of the present invention, and FIG.
Regarding changes in received radio field strength of the receiving device shown in the figure
FIG. 3 is a circuit diagram showing an embodiment in which the system block shown in FIG. 1 is applied to a monolithic semiconductor integrated circuit. Q ₃ ...Amplifying transistor, _Q4 , _Q5 ...Pair of transistors, _Q6 ...Circuit element, impedance means... _R4 , Load impedance means...
L ₁₀₂ , gain control voltage generation circuit...Q ₃₃ , R ₃₁ ,
_R32 , _R33 .

Claims (1)

[Claims] 1. An antenna 1, an RF amplification stage 2 for amplifying the RF signal of the antenna 1, a frequency conversion stage 4 connected to the output of the RF amplification stage 2, and an output from the frequency conversion stage 4. intermediate frequency amplification stages 6 and 8 for amplifying the obtained intermediate frequency signal; and for obtaining a gain control voltage from the output of the intermediate frequency amplification stages 6 and 8.
In a receiving device comprising AGC detection means 9 and 14 and in which the gain of the RF amplification stage 2 is controlled by the gain control voltage, a first gain control signal and a second gain control signal are detected by the gain control voltage. The generated gain control signal generation circuit Q ₃₃ , R ₃₁ , R ₃₂ , R ₃₃ ,
an amplifying transistor _Q3 , further comprising _Q1 , _Q7 , _Q8 , and having an emitter connected to a reference potential point via impedance means _R4 and a base to which the RF signal is supplied;
A pair of transistors Q ₄ , Q ₅ having emitters connected to the collector of Q ₃ , a load impedance L ₁₀₂ connected to the collector of one of the pair of transistors Q ₄ , _{Q 5} , and the amplification transistor Q ₃ .
The RF amplification stage 2 is constituted by a gain control circuit including a circuit element Q ₆ coupled to a circuit element Q ₆ and a capacitor C ₁₀₅ connected between the circuit element Q 6 and a reference potential point, The conductivity of the circuit element Q ₆ controlled by the control signal cooperates with the amplifying transistor Q ₃ and the capacitor C ₁₀₅ to control the RF signal amplitude level appearing at the load impedance L ₁₀₂ , thereby controlling the second gain. One of the pair of transistors _Q4 controlled by a control signal
The degree of conductivity occurs at the load impedance L ₁₀₂ above.
The RF signal amplitude level is controlled, and when the gain control voltage is at a low level, the first gain control signal and the second gain control signal are determined based on the conductivity of the circuit element _Q6 and the one Q of the pair of transistors. By setting the conductivities of both _Q4 to high conductivity, the RF amplification stage 2 is brought into a high gain state, and when the level of the gain control voltage increases, the first gain control signal lowers the conductivity of the circuit element _Q6. By doing so, the gain of the RF amplification stage 2 is lowered, and when the level of the gain control voltage increases thereafter, the gain of the second RF amplification stage 2 is lowered.
A receiving device characterized in that the gain control signal further reduces the gain of the RF amplification stage 2 by reducing the conductivity of the one _Q4 of the pair of transistors. 2 The impedance means of the RF amplification stage 2
R ₄ , the amplification transistor Q ₃ , the pair of transistors Q ₄ and Q ₅ , and the circuit element Q ₆ are configured within an integrated circuit, and the amplification transistor Q ₃ and the circuit element Q ₆ are configured within the integrated circuit. DC coupled above capacitor C ₁₀₅ and load impedance
2. The receiving device according to claim 1, wherein L ₁₀₂ is arranged outside the integrated circuit.