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JPS6142841U - Semiconductor chip pad - Google Patents

Semiconductor chip pad

Info

Publication number
JPS6142841U
JPS6142841U JP12735484U JP12735484U JPS6142841U JP S6142841 U JPS6142841 U JP S6142841U JP 12735484 U JP12735484 U JP 12735484U JP 12735484 U JP12735484 U JP 12735484U JP S6142841 U JPS6142841 U JP S6142841U
Authority
JP
Japan
Prior art keywords
semiconductor chip
region
pad
bonding region
auxiliary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12735484U
Other languages
Japanese (ja)
Inventor
俊雄 穴見
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP12735484U priority Critical patent/JPS6142841U/en
Publication of JPS6142841U publication Critical patent/JPS6142841U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例の平面図、第２図ないし第
５図はこの考案の変形例の平面図、第６図は半導体チッ
プの一般的外観を示す図、第７図は従来のパッドを示す
平面図である。 １０・・・パッド、１１，２１，３１，４１，５１・・
・ボンデイング領域、１３，２２，３３，４２，５２・
・・ボンデイング部分、１５・・・プローブ傷、６０・
・・チップ、６１・・・素子部分、６２・・・パッド。Fig. 1 is a plan view of an embodiment of this invention, Figs. 2 to 5 are plan views of modified examples of this invention, Fig. 6 is a diagram showing the general appearance of a semiconductor chip, and Fig. 7 is a conventional one. FIG. 3 is a plan view showing the pad of FIG. 10... Pad, 11, 21, 31, 41, 51...
・Bonding area, 13, 22, 33, 42, 52・
・・Bonding part, 15・Probe scratch, 60・
...Chip, 61...Element part, 62...Pad.

Claims (1)

【実用新案登録請求の範囲】 １ 所定の機能を有する素子部分を外部要素と接続する
ための金属領域を半導体チップ基板上に有して成る半導
体チップのパッドにおいて、前記金属領域は電極配線用
のボンデイング領域と、前記素子部分の前記機能を検査
する試験用の器具を当接する補助領域とを電気的接続状
態で近接して配設したことを特徴とする半導体チップの
パッド。 ２ 前記ボンデイング領域は矩形状であり、また前記補
助領域は前記ボンディング領域より小面積で前記ボンデ
ィング領域から突出した領域であることを特徴とする実
用新案登録請求の範囲第１項記載の半導体チップのパッ
ド。 ３ 前記ボンデイング領域及び前記補助領域は一方が他
方を囲周する様に配設したことを特徴とする実用新案登
録請求の範囲第１項記載の半導体チップのパッド。[Claims for Utility Model Registration] 1. In a semiconductor chip pad having a metal region on a semiconductor chip substrate for connecting an element portion having a predetermined function to an external element, the metal region is used for electrode wiring. A pad for a semiconductor chip, characterized in that a bonding region and an auxiliary region against which a test tool for testing the function of the element portion comes into contact are disposed in close electrical connection. 2. The semiconductor chip according to claim 1, wherein the bonding region has a rectangular shape, and the auxiliary region has a smaller area than the bonding region and protrudes from the bonding region. pad. 3. The pad of a semiconductor chip according to claim 1, wherein the bonding region and the auxiliary region are arranged so that one surrounds the other.
JP12735484U 1984-08-22 1984-08-22 Semiconductor chip pad Pending JPS6142841U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12735484U JPS6142841U (en) 1984-08-22 1984-08-22 Semiconductor chip pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12735484U JPS6142841U (en) 1984-08-22 1984-08-22 Semiconductor chip pad

Publications (1)

Publication Number Publication Date
JPS6142841U true JPS6142841U (en) 1986-03-19

Family

ID=30686000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12735484U Pending JPS6142841U (en) 1984-08-22 1984-08-22 Semiconductor chip pad

Country Status (1)

Country Link
JP (1) JPS6142841U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002190494A (en) * 2000-12-22 2002-07-05 Shinkawa Ltd Apparatus for bonding data setting and method therefor
JP2003347407A (en) * 1997-03-14 2003-12-05 Toshiba Corp Microwave integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347407A (en) * 1997-03-14 2003-12-05 Toshiba Corp Microwave integrated circuit device
JP2002190494A (en) * 2000-12-22 2002-07-05 Shinkawa Ltd Apparatus for bonding data setting and method therefor

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