JPS60106337U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS60106337U JPS60106337U JP19813483U JP19813483U JPS60106337U JP S60106337 U JPS60106337 U JP S60106337U JP 19813483 U JP19813483 U JP 19813483U JP 19813483 U JP19813483 U JP 19813483U JP S60106337 U JPS60106337 U JP S60106337U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- electrode wiring
- semiconductor equipment
- semiconductor
- directly connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は静電パルスによる素子破壊を説明する断面図、
第２図は本考案の実施例を示す断面図、第３図は不具合
な例の説明図、第４図〜第６図は本考案の異なる適用例
を示す断面図である。
図面で、１０，１２．１４は半導体基板、２゜は電極配
線、２２はくぼみの先端である。Figure 1 is a cross-sectional view illustrating element destruction due to electrostatic pulse.
FIG. 2 is a sectional view showing an embodiment of the present invention, FIG. 3 is an explanatory diagram of a defective example, and FIGS. 4 to 6 are sectional views showing different examples of application of the present invention. In the drawing, 10, 12, and 14 are semiconductor substrates, 2° is an electrode wiring, and 22 is the tip of a recess.
Claims (1)
着されそして外部端子ピンに直接接続される電極配線を
備える半導体装置において、該外部端子ピンに直接接続
する電極配線が被着する半導体基板部分にはくぼみが形
成され、該くぼみの全面に該電極配線を被着形成されて
なることを特徴とする半導体装置。In a semiconductor device comprising a semiconductor substrate on which a semiconductor element is formed, and an electrode wiring attached to the substrate and directly connected to an external terminal pin, a portion of the semiconductor substrate to which the electrode wiring directly connected to the external terminal pin is attached. 1. A semiconductor device characterized in that a recess is formed in the recess, and the electrode wiring is formed over the entire surface of the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19813483U JPS60106337U (en) | 1983-12-23 | 1983-12-23 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19813483U JPS60106337U (en) | 1983-12-23 | 1983-12-23 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60106337U true JPS60106337U (en) | 1985-07-19 |
Family
ID=30756863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19813483U Pending JPS60106337U (en) | 1983-12-23 | 1983-12-23 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60106337U (en) |
-
1983
- 1983-12-23 JP JP19813483U patent/JPS60106337U/en active Pending
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